--- a/genesis.c	Wed Dec 27 13:46:52 2017 -0800
+++ b/genesis.c	Sat Dec 30 18:27:06 2017 -0800
@@ -240,6 +240,7 @@
 static void z80_next_int_pulse(z80_context * z_context)
 {
 	genesis_context * gen = z_context->system;
+	vdp_run_context(gen->vdp, z_context->current_cycle);
 	z_context->int_pulse_start = vdp_next_vint_z80(gen->vdp);
 	z_context->int_pulse_end = z_context->int_pulse_start + Z80_INT_PULSE_MCLKS;
 	z_context->im2_vector = 0xFF;
@@ -344,6 +345,7 @@
 		context->sync_cycle = context->current_cycle + 1;
 	}
 	adjust_int_cycle(context, v_context);
+#ifdef USE_NATIVE
 	if (address) {
 		if (gen->header.enter_debugger) {
 			gen->header.enter_debugger = 0;
@@ -388,6 +390,7 @@
 			context->sync_cycle = context->current_cycle + 1;
 		}
 	}
+#endif
 #ifdef REFRESH_EMULATION
 	last_sync_cycle = context->current_cycle;
 #endif
@@ -910,11 +913,21 @@
 {
 	z80_context * context = vcontext;
 	genesis_context *gen = context->system;
+
 	if (gen->bus_busy) {
+#ifdef USE_NATIVE
 		context->current_cycle = context->sync_cycle;
+#else
+		context->m_icount = 0;
+#endif
 	}
+
 	//typical delay from bus arbitration
+#ifdef USE_NATIVE
 	context->current_cycle += 3 * MCLKS_PER_Z80;
+#else
+	context->m_icount -= 3;
+#endif
 	//TODO: add cycle for an access right after a previous one
 	//TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
 	//      Needs a new logic analyzer capture to get the actual delay on the 68K side
@@ -938,10 +951,18 @@
 	z80_context * context = vcontext;
 	genesis_context *gen = context->system;
 	if (gen->bus_busy) {
+#ifdef USE_NATIVE
 		context->current_cycle = context->sync_cycle;
+#else
+		context->m_icount = 0;
+#endif
 	}
 	//typical delay from bus arbitration
+#ifdef USE_NATIVE
 	context->current_cycle += 3 * MCLKS_PER_Z80;
+#else
+	context->m_icount -= 3;
+#endif
 	//TODO: add cycle for an access right after a previous one
 	//TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
 	//      Needs a new logic analyzer capture to get the actual delay on the 68K side
@@ -1038,7 +1059,7 @@
 	char *statepath = alloc_concat_m(3, parts);
 	deserialize_buffer state;
 	uint32_t pc = 0;
-	uint8_t ret;
+	uint8_t ret = 0;
 	if (load_from_file(&state, statepath)) {
 		genesis_deserialize(&state, gen);
 		free(state.data);
@@ -1046,13 +1067,17 @@
 		pc = gen->m68k->last_prefetch_address;
 		ret = 1;
 	} else {
+#ifdef USE_NATIVE
 		strcpy(statepath + strlen(statepath)-strlen("state"), "gst");
 		pc = load_gst(gen, statepath);
 		ret = pc != 0;
+#endif
 	}
+#ifdef USE_NATIVE
 	if (ret) {
 		gen->m68k->resume_pc = get_native_address_trans(gen->m68k, pc);
 	}
+#endif
 	free(statepath);
 	return ret;
 }
@@ -1072,24 +1097,30 @@
 			//HACK
 			pc = gen->m68k->last_prefetch_address;
 		} else {
+#ifdef USE_NATIVE
 			pc = load_gst(gen, statefile);
 			if (!pc) {
 				fatal_error("Failed to load save state %s\n", statefile);
 			}
+#endif
 		}
 		printf("Loaded %s\n", statefile);
+#ifdef USE_NATIVE
 		if (gen->header.enter_debugger) {
 			gen->header.enter_debugger = 0;
 			insert_breakpoint(gen->m68k, pc, gen->header.debugger_type == DEBUGGER_NATIVE ? debugger : gdb_debug_enter);
 		}
+#endif
 		adjust_int_cycle(gen->m68k, gen->vdp);
 		start_68k_context(gen->m68k, pc);
 	} else {
+#ifdef USE_NATIVE
 		if (gen->header.enter_debugger) {
 			gen->header.enter_debugger = 0;
 			uint32_t address = gen->cart[2] << 16 | gen->cart[3];
 			insert_breakpoint(gen->m68k, address, gen->header.debugger_type == DEBUGGER_NATIVE ? debugger : gdb_debug_enter);
 		}
+#endif
 		m68k_reset(gen->m68k);
 	}
 	handle_reset_requests(gen);