diff cpu_dsl.py @ 2666:38c281ef57b0

Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
author Michael Pavone <pavone@retrodev.com>
date Fri, 07 Mar 2025 23:40:58 -0800
parents 47e197d40ffe
children 6894a25ebfaa
line wrap: on
line diff
--- a/cpu_dsl.py	Fri Mar 07 21:45:53 2025 -0800
+++ b/cpu_dsl.py	Fri Mar 07 23:40:58 2025 -0800
@@ -1819,15 +1819,21 @@
 		if len(parts) == 3:
 			if parts[1].startswith('ptr'):
 				self.addPointer(parts[0], parts[1][3:], int(parts[2]))
+			elif parts[1].isdigit():
+				self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
 			else:
-				self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
+				#assume some other C type
+				self.addRegArray(parts[0], parts[1], int(parts[2]))
 		elif len(parts) > 2:
 			self.addRegArray(parts[0], int(parts[1]), parts[2:])
 		else:
 			if parts[1].startswith('ptr'):
 				self.addPointer(parts[0], parts[1][3:], 1)
+			elif parts[1].isdigit():
+				self.addReg(parts[0], int(parts[1]))
 			else:
-				self.addReg(parts[0], int(parts[1]))
+				#assume some other C type
+				self.addReg(parts[0], parts[1])
 		return self
 
 	def writeHeader(self, otype, hFile):
@@ -1847,11 +1853,17 @@
 			hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr))
 		for reg in self.regs:
 			if not self.isRegArrayMember(reg):
-				fieldList.append((self.regs[reg], 1, reg))
+				if type(self.regs[reg]) is int:
+					fieldList.append((self.regs[reg], 1, reg))
+				else:
+					hFile.write(f'\n\t{self.regs[reg]} {reg};')
 		for arr in self.regArrays:
 			size,regs = self.regArrays[arr]
 			if not type(regs) is int:
 				regs = len(regs)
+			if not type(size) is int:
+				hFile.write(f'\n\t{size} {arr}[{regs}];')
+				continue
 			fieldList.append((size, regs, arr))
 		fieldList.sort()
 		fieldList.reverse()