--- a/cpu_dsl.py	Sun Jan 27 14:37:37 2019 -0800
+++ b/cpu_dsl.py	Mon Jan 28 19:24:04 2019 -0800
@@ -324,14 +324,11 @@
 				output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format(
 					reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
 				))
-			elif prog.paramSize(prog.lastDst) > prog.paramSize(storage):
+			else:
 				reg = prog.resolveParam(storage, None, {})
-				output.append('\n\t{reg} = {res} != 0;'.format(
+				output.append('\n\t{reg} = {res} == 0;'.format(
 					reg = reg, res = lastDst
 				))
-			else:
-				reg = prog.resolveParam(storage, None, {})
-				output.append('\n\t{reg} = {res};'.format(reg = reg, res = lastDst))
 		elif calc == 'half-carry':
 			pass
 		elif calc == 'carry':
@@ -978,6 +975,7 @@
 		self.regs.writeHeader(otype, hFile)
 		hFile.write('\n}} {0}context;'.format(self.prefix))
 		hFile.write('\n')
+		hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type))
 		hFile.write('\n#endif //{0}_'.format(macro))
 		hFile.write('\n')
 		hFile.close()