diff cpu_dsl.py @ 2442:52cfc7b14dd2

Sugar for some basic conditionals in CPU DSL
author Michael Pavone <pavone@retrodev.com>
date Sun, 11 Feb 2024 20:41:28 -0800
parents 4435abe5db5e
children 461fffc226e0
line wrap: on
line diff
--- a/cpu_dsl.py	Sun Feb 11 20:15:00 2024 -0800
+++ b/cpu_dsl.py	Sun Feb 11 20:41:28 2024 -0800
@@ -19,6 +19,7 @@
 	'|': 'or',
 	'^': 'xor'
 }
+compareOps = {'>=U', '=', '!='}
 class Block:
 	def addOp(self, op):
 		pass
@@ -29,7 +30,12 @@
 			self.addOp(o)
 			return o
 		elif parts[0] == 'if':
-			o = If(self, parts[1])
+			if len(parts) == 4 and parts[2] in compareOps:
+				self.addOp(NormalOp(['cmp', parts[3], parts[1]]))
+				cond = parts[2]
+			else:
+				cond = parts[1]
+			o = If(self, cond)
 			self.addOp(o)
 			return o
 		elif parts[0] == 'end':