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diff cpu_dsl.py @ 1734:88fbc4e711fd

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Implemented the rest of the block move instructions in new Z80 core
author Michael Pavone <pavone@retrodev.com>
date Sun, 03 Feb 2019 10:40:41 -0800
parents 1f0a86f5e055
children ca2336469397
line wrap: on
line diff
--- a/cpu_dsl.py	Sat Feb 02 23:02:19 2019 -0800
+++ b/cpu_dsl.py	Sun Feb 03 10:40:41 2019 -0800
@@ -167,7 +167,7 @@
 			self.args.append((name, size))
 		elif op.op == 'local':
 			name = op.params[0]
-			size = op.params[1]
+			size = int(op.params[1])
 			self.locals[name] = size
 		else:
 			self.implementation.append(op)
@@ -339,7 +339,7 @@
 		if prog.carryFlowDst:
 			lastDst = prog.carryFlowDst
 		else:
-			lastDst = prog.resolveParam(prog.lastDst, None, {})
+			lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {})
 		storage = prog.flags.getStorage(flag)
 		if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
 			myRes = lastDst