diff cpu_dsl.py @ 1705:9ab64ef5cba0

Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
author Michael Pavone <pavone@retrodev.com>
date Mon, 28 Jan 2019 21:15:27 -0800
parents 89932fd29abd
children a16088324f30
line wrap: on
line diff
--- a/cpu_dsl.py	Mon Jan 28 20:54:55 2019 -0800
+++ b/cpu_dsl.py	Mon Jan 28 21:15:27 2019 -0800
@@ -304,7 +304,7 @@
 		else:
 			lastDst = prog.resolveParam(prog.lastDst, None, {})
 		storage = prog.flags.getStorage(flag)
-		if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half':
+		if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
 			myRes = lastDst
 			if calc == 'sign':
 				resultBit = prog.paramSize(prog.lastDst) - 1
@@ -313,6 +313,9 @@
 			elif calc == 'half':
 				resultBit = 4
 				myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
+			elif calc == 'overflow':
+				resultBit = prog.paramSize(prog.lastDst) - 1
+				myRes = '((~({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
 			else:
 				resultBit = int(resultBit)
 			if type(storage) is tuple:
@@ -347,9 +350,7 @@
 				reg = prog.resolveParam(storage, None, {})
 				output.append('\n\t{reg} = {res} == 0;'.format(
 					reg = reg, res = lastDst
-				))			
-		elif calc == 'overflow':
-			pass
+				))
 		elif calc == 'parity':
 			pass
 		else: