--- a/m68k.cpu	Sat Feb 15 19:11:40 2025 -0800
+++ b/m68k.cpu	Sat Feb 15 23:06:49 2025 -0800
@@ -1442,8 +1442,59 @@
 	invalid Z 3
 	local shift 8
 	and dregs.C 63 shift
-	lsr dregs.R shift dregs.R Z
-	update_flags XNZV0C
+	switch Z
+	case 2
+		if shift >=U 32
+			if shift = 32
+				lsr dregs.R 31 dregs.R Z
+				lsr dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsr dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 1
+		if shift >=U 16
+			if shift = 16
+				lsr dregs.R 15 dregs.R Z
+				lsr dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsr dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 0
+		if shift >=U 8
+			if shift = 8
+				lsr dregs.R 7 dregs.R Z
+				lsr dregs.R 1 dregs.R Z
+				update_flags XN0Z1V0C
+			else
+				dregs.R:Z = 0
+				update_flags X0N0Z1V0C0
+			end
+		else
+			lsr dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	end
 	add shift shift shift
 	switch Z
 	case 2
@@ -1496,38 +1547,59 @@
 1110CCC0ZZ100RRR asr_dn
 	invalid Z 3
 	local shift 32
-	local shift_cycles 32
 	and dregs.C 63 shift
-	shift_cycles = shift
-	if shift = 0
-		cmp 0 dregs.R Z
-		update_flags NZV0C0
-	else
-		switch Z
-		case 0
-			if shift >=U 9
-				shift = 8
-			end
-		case 1
-			if shift >=U 17
-				shift = 16
-			end
-		case 2
-			if shift >=U 33
-				shift = 32
+	switch Z
+	case 2
+		if shift >=U 32
+			asr dregs.R 31 dregs.R Z
+			asr dregs.R 1 dregs.R Z
+			update_flags NZV0
+			cflag = nflag
+			xflag = nflag
+		else
+			asr dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
 			end
 		end
-		asr dregs.R shift dregs.R Z
-		update_flags XNZV0C
+	case 1
+		if shift >=U 16
+			asr dregs.R 15 dregs.R Z
+			asr dregs.R 1 dregs.R Z
+			update_flags NZV0
+			cflag = nflag
+			xflag = nflag
+		else
+			asr dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
+	case 0
+		if shift >=U 8
+			asr dregs.R 7 dregs.R Z
+			asr dregs.R 1 dregs.R Z
+			update_flags NZV0
+			cflag = nflag
+			xflag = nflag
+		else
+			asr dregs.R shift dregs.R Z
+			update_flags NZV0C
+			if shift
+				xflag = cflag
+			end
+		end
 	end
-	shift_cycles += shift_cycles
+	shift += shift
 	switch Z
 	case 2
-		shift_cycles += 4
+		shift += 4
 	default
-		shift_cycles += 2
+		shift += 2
 	end
-	cycles shift_cycles
+	cycles shift
 	#TODO: should this happen before or after the majority of the shift?
 	m68k_prefetch