Mercurial > repos > blastem
diff m68k_core_x86.c @ 2620:b58ca7af1e60
Fix nbcd in old 68K core for non-register addressing modes
| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Fri, 21 Feb 2025 23:28:07 -0800 |
| parents | d74d3998482c |
| children | 7e86ec94c899 |
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--- a/m68k_core_x86.c Fri Feb 21 02:28:43 2025 -0800 +++ b/m68k_core_x86.c Fri Feb 21 23:28:07 2025 -0800 @@ -1471,6 +1471,11 @@ void translate_m68k_abcd_sbcd(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) { code_info *code = &opts->gen.code; + if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG && inst->dst.addr_mode != MODE_AREG_PREDEC) { + //destination is in memory so we need to preserve scratch2 for the write at the end + push_r(code, opts->gen.scratch2); + } + if (inst->op == M68K_NBCD) { if (dst_op->base != opts->gen.scratch2) { if (dst_op->mode == MODE_REG_DIRECT) { @@ -1496,10 +1501,6 @@ } } } - if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG && inst->dst.addr_mode != MODE_AREG_PREDEC) { - //destination is in memory so we need to preserve scratch2 for the write at the end - push_r(code, opts->gen.scratch2); - } //reg to reg takes 6 cycles, mem to mem is 4 cycles + all the operand fetch/writing (including 2 cycle predec penalty for first operand) cycles(&opts->gen, inst->dst.addr_mode != MODE_REG ? BUS : BUS + 2);