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Don't sync the 68K clock to the VDP clock unless the 68K had to wait for the VDP. This unfortunately breaks the direct color DMA demos, but should be more correct overall.
author Mike Pavone <pavone@retrodev.com>
date Sun, 19 May 2013 13:47:47 -0700
parents f664eeb55cb4
children 2455662378ed f7fe240a7da6
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    dc.l $0, start
start:
	moveq #36, d0
	bsr fib
	illegal
fib:
	cmp.l #2, d0
	blt base
	subq.l #1, d0
	move.l d0, -(a7)
	bsr fib
	move.l (a7), d1
	exg d0, d1
	move.l d1, (a7)
	subq.l #1, d0
	bsr fib
	move.l (a7)+, d1
	add.l d1, d0
	rts
base:
	moveq #1, d0
	rts