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Theoretically more correct timing of Z80 bus request
author Mike Pavone <pavone@retrodev.com>
date Wed, 18 Sep 2013 19:10:54 -0700
parents f664eeb55cb4
children 2455662378ed f7fe240a7da6
line wrap: on
line source

    dc.l $0, start
start:
	moveq #36, d0
	bsr fib
	illegal
fib:
	cmp.l #2, d0
	blt base
	subq.l #1, d0
	move.l d0, -(a7)
	bsr fib
	move.l (a7), d1
	exg d0, d1
	move.l d1, (a7)
	subq.l #1, d0
	bsr fib
	move.l (a7)+, d1
	add.l d1, d0
	rts
base:
	moveq #1, d0
	rts