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Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
author Michael Pavone <pavone@retrodev.com>
date Sun, 11 Nov 2018 22:39:29 -0800
parents f7fe240a7da6
children b7ecd0d6a77b
line wrap: on
line source

    dc.l $0, start
start:
	moveq #42, d0
	bsr fib
	reset
fib:
	cmp.l #2, d0
	blt base
	subq.l #1, d0
	move.l d0, -(a7)
	bsr fib
	move.l (a7), d1
	exg d0, d1
	move.l d1, (a7)
	subq.l #1, d0
	bsr fib
	move.l (a7)+, d1
	add.l d1, d0
	rts
base:
	moveq #1, d0
	rts