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Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Fri, 16 Nov 2018 19:56:24 -0800, by Michael Pavone
Implemented left column blank register bit in mode 5
Thu, 15 Nov 2018 22:21:09 -0800, by Michael Pavone
Initial stab at CRAM debug in a detached window
Wed, 14 Nov 2018 22:16:35 -0800, by Michael Pavone
Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Sun, 11 Nov 2018 22:39:29 -0800, by Michael Pavone
Make sure M68K sync and target cycles are updated after loading a savestate. Fixes an issue in which loading a savestate would result in things being unresponsive until emulation cycle caught up to whatever the pre-state load sync cycle was
Sun, 11 Nov 2018 11:33:38 -0800, by Mike Pavone
Fix edge case in DRC audio path
Sat, 10 Nov 2018 15:27:39 -0800, by Michael Pavone
Added VRAM debug window
Fri, 09 Nov 2018 20:16:09 -0800, by Michael Pavone
Use SDL_GL_MakeCurrent to make the SDL renderer API windows play nice with GL windows
Fri, 09 Nov 2018 09:26:07 -0800, by Michael Pavone

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