Mercurial > repos > blastem
graph
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Initial implementation of sprite overflow and sprite collision status register flagsMon, 07 Oct 2013 10:02:08 -0700, by Mike Pavone
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Add support for UI bindings on gamepad buttons and dpadsFri, 04 Oct 2013 20:16:18 -0700, by Mike Pavone
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Merged OpenGL branchSun, 27 Oct 2013 22:08:02 -0700, by Mike Pavone
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Update opengl branch from default. Fix build breakage unrelated to merge openglSat, 26 Oct 2013 22:38:47 -0700, by Mike Pavone
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Add an FPS counter to the title barThu, 03 Oct 2013 21:22:05 -0700, by Mike Pavone
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Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashingThu, 03 Oct 2013 21:21:47 -0700, by Mike Pavone
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Add support for test instruction to x86 generator libraryThu, 03 Oct 2013 21:20:29 -0700, by Mike Pavone
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Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a buttonTue, 01 Oct 2013 23:51:16 -0700, by Mike Pavone
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Theoretically more correct timing of Z80 bus requestWed, 18 Sep 2013 19:10:54 -0700, by Mike Pavone
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Set VBLANK flag in status register when display is disabledTue, 17 Sep 2013 19:10:00 -0700, by Mike Pavone
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Implement HV counter latchTue, 17 Sep 2013 09:45:14 -0700, by Mike Pavone
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Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40Tue, 17 Sep 2013 00:42:49 -0700, by Mike Pavone
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Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.Tue, 17 Sep 2013 00:11:45 -0700, by Mike Pavone
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Partial fix for DMA copyMon, 16 Sep 2013 09:44:22 -0700, by Mike Pavone
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Clear the low 2 bits of CD when a register is written toSun, 15 Sep 2013 23:49:09 -0700, by Mike Pavone
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Don't allow register writes to regs above when in Mode 4Sun, 15 Sep 2013 23:40:18 -0700, by Mike Pavone
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Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11Sun, 15 Sep 2013 23:33:24 -0700, by Mike Pavone
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Implement undocumented 8-bit VRAM readSun, 15 Sep 2013 23:00:17 -0700, by Mike Pavone
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Fix VSRAM readsSun, 15 Sep 2013 22:43:01 -0700, by Mike Pavone
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Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properlySun, 15 Sep 2013 22:20:43 -0700, by Mike Pavone