| Tue, 17 Sep 2013 09:45:14 -0700 |
Mike Pavone |
Implement HV counter latch
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| Tue, 17 Sep 2013 00:42:49 -0700 |
Mike Pavone |
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
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| Tue, 17 Sep 2013 00:11:45 -0700 |
Mike Pavone |
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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| Mon, 16 Sep 2013 09:44:22 -0700 |
Mike Pavone |
Partial fix for DMA copy
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| Sun, 15 Sep 2013 23:49:09 -0700 |
Mike Pavone |
Clear the low 2 bits of CD when a register is written to
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| Sun, 15 Sep 2013 23:40:18 -0700 |
Mike Pavone |
Don't allow register writes to regs above when in Mode 4
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| Sun, 15 Sep 2013 23:33:24 -0700 |
Mike Pavone |
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
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| Sun, 15 Sep 2013 23:00:17 -0700 |
Mike Pavone |
Implement undocumented 8-bit VRAM read
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| Sun, 15 Sep 2013 22:43:01 -0700 |
Mike Pavone |
Fix VSRAM reads
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| Sun, 15 Sep 2013 22:20:43 -0700 |
Mike Pavone |
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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| Fri, 13 Sep 2013 19:22:46 -0700 |
Mike Pavone |
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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| Tue, 10 Sep 2013 23:31:08 -0700 |
Mike Pavone |
Added copyright notice to source files and added GPL license text in COPYING
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| Tue, 10 Sep 2013 09:55:12 -0700 |
Mike Pavone |
Fix timing of backdrop rendering when the display is turned off
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| Tue, 10 Sep 2013 00:30:39 -0700 |
Mike Pavone |
Merge
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| Tue, 10 Sep 2013 00:29:46 -0700 |
Mike Pavone |
Implement FIFO latency and improve DMA accuracy
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| Sun, 08 Sep 2013 20:48:33 -0700 |
Mike Pavone |
Revert change to VBLANK flag timing based on new direct color DMA test
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| Mon, 02 Sep 2013 01:02:18 -0700 |
Mike Pavone |
Fix per-column scrolling bug
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| Mon, 02 Sep 2013 00:20:56 -0700 |
Mike Pavone |
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
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| Sun, 01 Sep 2013 14:27:17 -0700 |
Mike Pavone |
Merge
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| Fri, 26 Jul 2013 19:55:04 -0700 |
Mike Pavone |
Added support for saving savestates. Added gst savestate format test harness
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| Sun, 01 Sep 2013 12:11:28 -0700 |
Mike Pavone |
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
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| Tue, 16 Jul 2013 23:16:14 -0700 |
Mike Pavone |
Add address/cd registers to VDP debug message
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| Mon, 15 Jul 2013 23:07:45 -0700 |
Mike Pavone |
Restore one of the VDP debugging modes
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| Fri, 12 Jul 2013 19:11:55 -0700 |
Mike Pavone |
Implement the scroll ring buffer properly without memcpy
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| Sun, 30 Jun 2013 21:45:23 -0700 |
Mike Pavone |
Refactor duplicated CRAM writing code and fix a bug in the process
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| Sun, 30 Jun 2013 11:45:58 -0700 |
Mike Pavone |
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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| Sat, 29 Jun 2013 17:15:08 -0700 |
Mike Pavone |
Add support for loading GST format savestates
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| Sun, 23 Jun 2013 12:27:11 -0700 |
Mike Pavone |
Fix window layer in double res interlace mode
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| Sun, 23 Jun 2013 10:17:40 -0700 |
Mike Pavone |
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
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| Sun, 23 Jun 2013 09:17:19 -0700 |
Mike Pavone |
Fix vscroll calculation in double resultion interlace mode
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