| Sun, 06 Jan 2013 15:20:23 -0800 |
Mike Pavone |
Implement negx
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| Sun, 06 Jan 2013 14:41:26 -0800 |
Mike Pavone |
Implement movep
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| Sun, 06 Jan 2013 14:00:45 -0800 |
Mike Pavone |
Implement EORI CCR/SR
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| Sun, 06 Jan 2013 13:58:33 -0800 |
Mike Pavone |
Implement RTR
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| Sun, 06 Jan 2013 13:42:13 -0800 |
Mike Pavone |
Fix a bunch of addressing modes in movem when a register list is the destination
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| Sun, 06 Jan 2013 12:17:10 -0800 |
Mike Pavone |
Minor optimization and a cycle count fix to lea
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| Sun, 06 Jan 2013 10:54:45 -0800 |
Mike Pavone |
Initialize status register to proper value on startup
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| Sat, 05 Jan 2013 22:59:51 -0800 |
Mike Pavone |
Fix certain address modes with lea when the destination is not a native register
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| Sat, 05 Jan 2013 02:18:31 -0800 |
Mike Pavone |
Implement more movem modes src
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| Sat, 05 Jan 2013 01:55:11 -0800 |
Mike Pavone |
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
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| Sat, 05 Jan 2013 01:31:28 -0800 |
Mike Pavone |
FIx movem when src is reg list and dst is not a areg predec mode
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| Sat, 05 Jan 2013 00:53:50 -0800 |
Mike Pavone |
Fix predec address mode when used as source
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| Fri, 04 Jan 2013 23:52:20 -0800 |
Mike Pavone |
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
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| Fri, 04 Jan 2013 23:25:23 -0800 |
Mike Pavone |
Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
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| Fri, 04 Jan 2013 23:21:07 -0800 |
Mike Pavone |
Don't use the native call stack for M68K calls by default
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| Fri, 04 Jan 2013 22:51:01 -0800 |
Mike Pavone |
Small fix for bit instructions
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| Thu, 03 Jan 2013 22:49:21 -0800 |
Mike Pavone |
Implement TRAP (untested)
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| Thu, 03 Jan 2013 22:07:40 -0800 |
Mike Pavone |
Implement MULU/MULS and DIVU/DIVS
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| Tue, 01 Jan 2013 09:40:17 -0800 |
Mike Pavone |
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
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| Mon, 31 Dec 2012 20:09:09 -0800 |
Mike Pavone |
Implement most of the "X" instructions
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| Sun, 30 Dec 2012 09:55:07 -0800 |
Mike Pavone |
Add support for pc indexed addressing mode to lea
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| Sun, 30 Dec 2012 07:52:44 -0800 |
Mike Pavone |
Support more address modes for jmp
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| Sat, 29 Dec 2012 23:40:30 -0800 |
Mike Pavone |
Fix swap
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| Sat, 29 Dec 2012 23:08:14 -0800 |
Mike Pavone |
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
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| Sat, 29 Dec 2012 22:22:53 -0800 |
Mike Pavone |
Fix check in translate_m68k_src that deals with instructions for which both operands are registers that are not mapped to a native x86-64 register
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| Sat, 29 Dec 2012 22:11:28 -0800 |
Mike Pavone |
Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
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| Sat, 29 Dec 2012 21:55:42 -0800 |
Mike Pavone |
Some fixes for translating code in located in RAM
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| Sat, 29 Dec 2012 21:10:07 -0800 |
Mike Pavone |
Implement the rest of the bit instructions
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| Sat, 29 Dec 2012 20:33:39 -0800 |
Mike Pavone |
Implemented ROL and ROR
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| Sat, 29 Dec 2012 12:52:19 -0800 |
Mike Pavone |
Fix logic for switching between USP and SSP
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