Mercurial > repos > blastem

log cpu_dsl.py @ 2591:563d05355a12

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
less more | (0) -12 tip
age author description
Sun, 09 Feb 2025 14:15:22 -0800 Michael Pavone Cut down on code bloat in 68K core a little
Sun, 09 Feb 2025 02:56:50 -0800 Michael Pavone Low confidence fix for edge case in CPU DSL not currently hit
Sat, 08 Feb 2025 20:04:18 -0800 Michael Pavone Implement divs and divu in new CPU core
Sat, 08 Feb 2025 12:51:35 -0800 Michael Pavone Better unimplemented instruction error message in CPU DSL
Sat, 08 Feb 2025 11:40:42 -0800 Michael Pavone Get 68K interrupts working in new CPU core
Fri, 07 Feb 2025 19:58:20 -0800 Michael Pavone Fix rol and ror in new CPU core
Fri, 07 Feb 2025 08:57:24 -0800 Michael Pavone WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Sat, 25 Jan 2025 21:25:01 -0800 Michael Pavone Implement exg, muls and mulu in new 68K core
Tue, 16 Jul 2024 20:21:08 -0700 Michael Pavone Partially functional asr/asl implementations in new 68K core
Tue, 30 Apr 2024 22:32:08 -0700 Michael Pavone Get blastem compiling with new 68K core
Tue, 30 Apr 2024 00:02:14 -0700 Michael Pavone Make some progress on compiling full emulator with new 68K core
Mon, 29 Apr 2024 22:57:33 -0700 Michael Pavone Fix constant propagation for sext instruction
less more | (0) -12 tip