| Sun, 06 Aug 2017 00:06:36 -0700 |
Michael Pavone |
WIP - New savestate format
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| Fri, 19 May 2017 20:27:35 -0700 |
Michael Pavone |
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
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| Mon, 24 Apr 2017 20:49:31 -0700 |
Michael Pavone |
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
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| Tue, 28 Mar 2017 00:13:35 -0700 |
Michael Pavone |
Implemented M68K trace mode. Some edge cases/SR update paths still need work
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| Sat, 25 Mar 2017 00:21:32 -0700 |
Michael Pavone |
Prevent blowing past our native translated instruction size of 255 bytes when translating movem with a large register list. Fixes bug in which Fantastic Dizzy was completely broken on 32-bit builds
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| Thu, 23 Feb 2017 00:08:37 -0800 |
Michael Pavone |
WIP support for XBAND mapper hardware
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| Wed, 28 Dec 2016 20:39:27 -0800 |
Michael Pavone |
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
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| Mon, 19 Dec 2016 13:28:18 -0800 |
Michael Pavone |
Mostly working changes to allow support for multiple emulated system types in main blastem program
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| Mon, 28 Nov 2016 22:45:46 -0800 |
Michael Pavone |
Clean up symbol visiblity and delete a ltitle bit of dead code
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| Sat, 05 Nov 2016 00:23:11 -0700 |
Michael Pavone |
Get Jaguar video interrupt working
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| Sun, 16 Oct 2016 18:25:18 -0700 |
Michael Pavone |
Initial stab at implementing the Jaguar object processor
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| Thu, 06 Oct 2016 09:34:31 -0700 |
Michael Pavone |
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
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| Sat, 30 Apr 2016 09:45:53 -0700 |
Michael Pavone |
Fix 68K interrupt handling some more. Fatal Rewind is working again.
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| Wed, 27 Apr 2016 21:39:17 -0700 |
Michael Pavone |
Implemented IR and undefined bits of info word for address error exception frames
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| Tue, 26 Apr 2016 23:13:37 -0700 |
Michael Pavone |
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
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