log cpu_dsl.py @ 1999:7a6835c02db0

age author description
Sat, 13 Jun 2020 00:37:22 -0700 Michael Pavone Somewhat buggy implementations of shift instructions in new 68K core
Thu, 23 Apr 2020 20:57:14 -0700 Michael Pavone Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Sat, 21 Sep 2019 10:48:10 -0700 Michael Pavone Implement interrupts in call dispatch mode in CPU DSL
Thu, 18 Apr 2019 19:47:50 -0700 Michael Pavone WIP new 68K core using CPU DSL
Wed, 20 Feb 2019 00:34:52 -0800 Michael Pavone Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Tue, 19 Feb 2019 22:51:33 -0800 Michael Pavone Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Fri, 15 Feb 2019 23:58:34 -0800 Michael Pavone Basic support for string operands in CPU DSL
Tue, 12 Feb 2019 09:58:04 -0800 Michael Pavone Integration of new Z80 core is sort of working now
Sun, 10 Feb 2019 11:58:23 -0800 Michael Pavone Initial attempt at interrupts in new Z80 core and integrating it into main executable
Sat, 09 Feb 2019 11:34:31 -0800 Michael Pavone Optimization to memory access in new Z80 core
Fri, 08 Feb 2019 23:09:58 -0800 Michael Pavone Added option to CPU DSL to produce a threaded interpreter using computed goto
Thu, 07 Feb 2019 09:43:25 -0800 Michael Pavone Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Wed, 06 Feb 2019 09:13:24 -0800 Michael Pavone Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Wed, 06 Feb 2019 08:54:09 -0800 Michael Pavone Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Tue, 05 Feb 2019 19:29:54 -0800 Michael Pavone Fixed half-carry flag calcuation for adc/sbc in new Z80 core