| Mon, 16 Sep 2013 09:44:22 -0700 |
Mike Pavone |
Partial fix for DMA copy
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| Sun, 15 Sep 2013 23:49:09 -0700 |
Mike Pavone |
Clear the low 2 bits of CD when a register is written to
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| Sun, 15 Sep 2013 23:40:18 -0700 |
Mike Pavone |
Don't allow register writes to regs above when in Mode 4
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| Sun, 15 Sep 2013 23:33:24 -0700 |
Mike Pavone |
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
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| Sun, 15 Sep 2013 23:00:17 -0700 |
Mike Pavone |
Implement undocumented 8-bit VRAM read
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| Sun, 15 Sep 2013 22:43:01 -0700 |
Mike Pavone |
Fix VSRAM reads
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| Sun, 15 Sep 2013 22:20:43 -0700 |
Mike Pavone |
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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| Fri, 13 Sep 2013 19:22:46 -0700 |
Mike Pavone |
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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| Tue, 10 Sep 2013 23:31:08 -0700 |
Mike Pavone |
Added copyright notice to source files and added GPL license text in COPYING
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| Tue, 10 Sep 2013 09:55:12 -0700 |
Mike Pavone |
Fix timing of backdrop rendering when the display is turned off
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| Tue, 10 Sep 2013 00:30:39 -0700 |
Mike Pavone |
Merge
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| Tue, 10 Sep 2013 00:29:46 -0700 |
Mike Pavone |
Implement FIFO latency and improve DMA accuracy
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| Sun, 08 Sep 2013 20:48:33 -0700 |
Mike Pavone |
Revert change to VBLANK flag timing based on new direct color DMA test
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| Mon, 02 Sep 2013 01:02:18 -0700 |
Mike Pavone |
Fix per-column scrolling bug
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| Mon, 02 Sep 2013 00:20:56 -0700 |
Mike Pavone |
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
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