Fri, 18 Mar 2022 20:49:07 -0700 |
Michael Pavone |
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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Sun, 13 Feb 2022 22:52:52 -0800 |
Michael Pavone |
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
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Thu, 05 Aug 2021 09:43:29 -0700 |
Michael Pavone |
Fix compile error post-merge
mame_interp
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Thu, 05 Aug 2021 09:29:33 -0700 |
Michael Pavone |
Merge from default
mame_interp
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Sun, 07 Mar 2021 22:43:51 -0800 |
Michael Pavone |
Fix bug in handling of MMAP_CODE regions smaller than 16KB
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Sat, 09 May 2020 23:39:44 -0700 |
Michael Pavone |
Merge from default
mame_interp
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Sun, 03 May 2020 23:24:03 -0700 |
Michael Pavone |
Apply fixes to helper functions in backend.c from interp branch
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Thu, 30 Apr 2020 23:30:22 -0700 |
Michael Pavone |
Remove usage of GCC pointer arithmetic on void * extension
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Sat, 18 Apr 2020 11:42:53 -0700 |
Michael Pavone |
Merge from default
mame_interp
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Thu, 18 Apr 2019 19:47:50 -0700 |
Michael Pavone |
WIP new 68K core using CPU DSL
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Tue, 12 Mar 2019 21:57:35 -0700 |
Michael Pavone |
Fix a couple issues in manual memory map read/write functions
mame_interp
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Fri, 01 Mar 2019 14:17:29 -0800 |
Michael Pavone |
Merge from default
mame_interp
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Tue, 12 Feb 2019 09:58:04 -0800 |
Michael Pavone |
Integration of new Z80 core is sort of working now
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Mon, 28 Jan 2019 19:24:04 -0800 |
Michael Pavone |
Fix zero flag calculation in CPU DSL
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Thu, 24 Jan 2019 19:15:59 -0800 |
Michael Pavone |
Merge from default
mame_interp
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Wed, 16 Jan 2019 09:49:18 -0800 |
Michael Pavone |
Don't subtract chunk start from address in read_word as this is inconsistent with other consumers of memory map definitions. Fixes graphical corruption in NBA Jam TE and possibly other titles that use the Acclaim mapper with a 32Mbit ROM
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Tue, 25 Dec 2018 11:12:26 -0800 |
Michael Pavone |
Merge from default
mame_interp
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Wed, 31 Jan 2018 22:05:10 -0800 |
Michael Pavone |
Made the NOR flash emulation a bit more flexible, but not yet flexible enough to properly support the flash chip in the MegaWiFi cart
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Sat, 30 Dec 2017 18:27:06 -0800 |
Michael Pavone |
Added MAME Z80 core, re-enabled 68K tracing in Musashi core, disabled a bunch of code gen stuff when using interpreters from MAME
mame_interp
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Wed, 27 Dec 2017 13:46:52 -0800 |
Michael Pavone |
Super hacky integration of the version of Musashi from MAME
mame_interp
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Mon, 26 Jun 2017 21:12:46 -0700 |
Michael Pavone |
Fix a silly variable shadowing bug in read_word
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Mon, 03 Apr 2017 20:48:13 -0700 |
Michael Pavone |
Improved printing of word at absolute address to support reading from all address types. Implemented support for printing the value pointed to by a register. Removed abuse of read_dma_value in internal debugger.
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Mon, 02 Jan 2017 23:35:40 -0800 |
Michael Pavone |
Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
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Wed, 28 Dec 2016 20:39:27 -0800 |
Michael Pavone |
Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
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Tue, 04 Oct 2016 18:30:24 -0700 |
Michael Pavone |
Add a new memory map flag to support an auxilliary buffer for translating code from MMAP_PTR_IDX chunks for which the pointer is null
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Wed, 14 Jan 2015 09:38:54 -0800 |
Michael Pavone |
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
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Thu, 01 Jan 2015 17:31:59 -0800 |
Michael Pavone |
Fix some issues with 68K instruction retranslation
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Thu, 01 Jan 2015 14:36:55 -0800 |
Michael Pavone |
Remove some of the hard coded assumptions about the memory map from the CPU cores
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Mon, 24 Feb 2014 01:30:16 -0800 |
Mike Pavone |
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
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Mon, 24 Feb 2014 00:50:15 -0800 |
Mike Pavone |
Rename x86_backend.h and x86_backend.c to backend.h and backend.c respectively
base
x86_backend.c@b1bff27ef676
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