log vdp.c @ 678:a7971650c04e

age author description
Sun, 04 Jan 2015 12:24:34 -0800 Michael Pavone Adjusted h40_hsync_cycles so that lines actually take 3420 mclks. Fixed vdp_cycles_next_line to take h40_sync_cycles into account
Sun, 14 Dec 2014 18:14:50 -0800 Michael Pavone Fix the HV counter and adjust the slots of certain VDP events
Thu, 14 Aug 2014 09:38:32 -0700 Michael Pavone Small fix to display of DMA source address in vr debug command
Wed, 18 Jun 2014 16:39:42 -0700 Michael Pavone Remove debug printf that escaped into my previous commit
Wed, 18 Jun 2014 16:30:19 -0700 Michael Pavone Fix most of the breakage caused by the vcounter/hcounter changes
Tue, 17 Jun 2014 19:01:01 -0700 Michael Pavone Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Mon, 16 Jun 2014 19:13:28 -0700 Michael Pavone Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Sat, 08 Feb 2014 23:37:09 -0800 Mike Pavone Initial GDB remote debugging support. Lacks some features, but breakpoints and basic inspection of registers and memory work.
Mon, 06 Jan 2014 22:54:05 -0800 Michael Pavone The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Thu, 31 Oct 2013 00:28:27 -0700 Mike Pavone Small optimization for H40 mode
Tue, 29 Oct 2013 00:03:11 -0700 Mike Pavone Merge
Mon, 07 Oct 2013 10:02:08 -0700 Mike Pavone Initial implementation of sprite overflow and sprite collision status register flags
Sun, 27 Oct 2013 01:29:50 -0700 Mike Pavone Basic OpenGL rendering is working opengl
Tue, 17 Sep 2013 19:10:00 -0700 Mike Pavone Set VBLANK flag in status register when display is disabled
Tue, 17 Sep 2013 09:45:14 -0700 Mike Pavone Implement HV counter latch
Tue, 17 Sep 2013 00:42:49 -0700 Mike Pavone Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
Tue, 17 Sep 2013 00:11:45 -0700 Mike Pavone Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mon, 16 Sep 2013 09:44:22 -0700 Mike Pavone Partial fix for DMA copy
Sun, 15 Sep 2013 23:49:09 -0700 Mike Pavone Clear the low 2 bits of CD when a register is written to
Sun, 15 Sep 2013 23:40:18 -0700 Mike Pavone Don't allow register writes to regs above when in Mode 4
Sun, 15 Sep 2013 23:33:24 -0700 Mike Pavone Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Sun, 15 Sep 2013 23:00:17 -0700 Mike Pavone Implement undocumented 8-bit VRAM read
Sun, 15 Sep 2013 22:43:01 -0700 Mike Pavone Fix VSRAM reads
Sun, 15 Sep 2013 22:20:43 -0700 Mike Pavone Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Fri, 13 Sep 2013 19:22:46 -0700 Mike Pavone Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Tue, 10 Sep 2013 23:31:08 -0700 Mike Pavone Added copyright notice to source files and added GPL license text in COPYING
Tue, 10 Sep 2013 09:55:12 -0700 Mike Pavone Fix timing of backdrop rendering when the display is turned off
Tue, 10 Sep 2013 00:30:39 -0700 Mike Pavone Merge
Tue, 10 Sep 2013 00:29:46 -0700 Mike Pavone Implement FIFO latency and improve DMA accuracy
Sun, 08 Sep 2013 20:48:33 -0700 Mike Pavone Revert change to VBLANK flag timing based on new direct color DMA test