| Tue, 17 Jun 2014 19:01:01 -0700 |
Michael Pavone |
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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| Mon, 16 Jun 2014 19:13:28 -0700 |
Michael Pavone |
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
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| Sat, 08 Feb 2014 23:37:09 -0800 |
Mike Pavone |
Initial GDB remote debugging support. Lacks some features, but breakpoints and basic inspection of registers and memory work.
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| Mon, 06 Jan 2014 22:54:05 -0800 |
Michael Pavone |
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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| Thu, 31 Oct 2013 00:28:27 -0700 |
Mike Pavone |
Small optimization for H40 mode
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| Tue, 29 Oct 2013 00:03:11 -0700 |
Mike Pavone |
Merge
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| Mon, 07 Oct 2013 10:02:08 -0700 |
Mike Pavone |
Initial implementation of sprite overflow and sprite collision status register flags
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| Sun, 27 Oct 2013 01:29:50 -0700 |
Mike Pavone |
Basic OpenGL rendering is working
opengl
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| Tue, 17 Sep 2013 19:10:00 -0700 |
Mike Pavone |
Set VBLANK flag in status register when display is disabled
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| Tue, 17 Sep 2013 09:45:14 -0700 |
Mike Pavone |
Implement HV counter latch
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| Tue, 17 Sep 2013 00:42:49 -0700 |
Mike Pavone |
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
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| Tue, 17 Sep 2013 00:11:45 -0700 |
Mike Pavone |
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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| Mon, 16 Sep 2013 09:44:22 -0700 |
Mike Pavone |
Partial fix for DMA copy
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| Sun, 15 Sep 2013 23:49:09 -0700 |
Mike Pavone |
Clear the low 2 bits of CD when a register is written to
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| Sun, 15 Sep 2013 23:40:18 -0700 |
Mike Pavone |
Don't allow register writes to regs above when in Mode 4
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