| Sat, 19 Mar 2022 15:50:45 -0700 |
Michael Pavone |
Fix some dynarec code invalidation issues
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| Fri, 18 Mar 2022 20:49:07 -0700 |
Michael Pavone |
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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| Thu, 17 Mar 2022 22:41:42 -0700 |
Michael Pavone |
Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
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| Sun, 13 Feb 2022 22:52:52 -0800 |
Michael Pavone |
Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size
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| Sun, 30 Jan 2022 19:56:09 -0800 |
Michael Pavone |
Fix error in code write detection introduced from "wide" jcc change
segacd
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| Tue, 18 Jan 2022 00:03:50 -0800 |
Michael Pavone |
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
segacd
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| Sun, 07 Mar 2021 22:43:51 -0800 |
Michael Pavone |
Fix bug in handling of MMAP_CODE regions smaller than 16KB
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| Sun, 31 Dec 2017 14:08:47 -0800 |
Michael Pavone |
Fix accidental add to RSP with SZ_D and SZ_PTR. Using SZ_D breakse when the stack is located outside of the 32-bit addressable range
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| Wed, 13 Sep 2017 21:06:25 -0700 |
Michael Pavone |
Preserve original address when retranslating instructions instead of switching to the lowest alias
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| Tue, 03 Jan 2017 21:18:42 -0800 |
Michael Pavone |
Fix RAM flag offset calculation to take into account the existence of non-writeable MMAP_CODE chunks
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| Thu, 22 Dec 2016 10:51:33 -0800 |
Michael Pavone |
More cleanup in preparation for SMS/Mark III support
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| Wed, 14 Dec 2016 23:26:12 -0800 |
Michael Pavone |
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
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| Mon, 12 Dec 2016 19:21:22 -0800 |
Michael Pavone |
Fix to the fix of handling of self modifying code. Was ORing the base address with the wrong register before calling the modified code handler
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| Thu, 06 Oct 2016 22:25:12 -0700 |
Michael Pavone |
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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