| Thu, 27 Dec 2012 22:35:26 -0800 |
Mike Pavone |
Some fixes to add/addx sub/subx decoding
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| Thu, 27 Dec 2012 21:19:58 -0800 |
Mike Pavone |
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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| Thu, 27 Dec 2012 18:47:33 -0800 |
Mike Pavone |
Fix decoding bug for addq/subq
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| Thu, 27 Dec 2012 18:21:10 -0800 |
Mike Pavone |
Implement EXT, add some fixes to LINK/UNLK
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| Thu, 27 Dec 2012 10:10:23 -0800 |
Mike Pavone |
Fix decoding bug in addq/subq
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| Wed, 26 Dec 2012 22:13:31 -0800 |
Mike Pavone |
Fix decoding of and
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| Fri, 21 Dec 2012 22:24:45 -0800 |
Mike Pavone |
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
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| Thu, 20 Dec 2012 09:12:24 -0800 |
Mike Pavone |
Fix disassembly of reg list in MOVEM when the reg list is the destination
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| Thu, 20 Dec 2012 09:08:13 -0800 |
Mike Pavone |
Fix decoding and disassembly of MOVEM
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| Wed, 19 Dec 2012 20:53:45 -0800 |
Mike Pavone |
Print out large immediate values in hex rather than decimal form
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| Wed, 19 Dec 2012 20:23:59 -0800 |
Mike Pavone |
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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| Tue, 18 Dec 2012 23:55:10 -0800 |
Mike Pavone |
Fix operand order for AND instructions
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| Tue, 18 Dec 2012 02:16:42 -0800 |
Mike Pavone |
Get Flavio's color bar demo kind of sort of working
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| Sat, 15 Dec 2012 23:01:32 -0800 |
Mike Pavone |
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
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| Thu, 13 Dec 2012 09:47:40 -0800 |
Mike Pavone |
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
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| Wed, 12 Dec 2012 20:18:06 -0800 |
Mike Pavone |
Add support for dbcc instruction
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| Tue, 04 Dec 2012 19:13:12 -0800 |
Mike Pavone |
M68K to x86 translation works for a limited subset of instructions and addressing modes
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| Tue, 27 Nov 2012 22:43:32 -0800 |
Mike Pavone |
Make x86 generator generic with respect to operand size for immediate parameters.
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| Thu, 15 Nov 2012 22:15:43 -0800 |
Mike Pavone |
Improve disassembly. FIx some decoding bugs.
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| Thu, 15 Nov 2012 00:52:53 -0800 |
Mike Pavone |
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
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| Wed, 14 Nov 2012 23:04:55 -0800 |
Mike Pavone |
Implement OR_DIV_SBCD group in decoder
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| Wed, 14 Nov 2012 09:24:40 -0800 |
Mike Pavone |
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
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| Tue, 13 Nov 2012 18:26:43 -0800 |
Mike Pavone |
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
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| Fri, 09 Nov 2012 22:01:26 -0800 |
Mike Pavone |
Finish bit/movep/immediate group except for 68020 instructions
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| Tue, 06 Nov 2012 02:04:42 -0800 |
Mike Pavone |
More bit and immediate instructions
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| Sun, 04 Nov 2012 23:43:03 -0800 |
Mike Pavone |
Add support for some bit instructions and a few others in the same "category"
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| Sat, 03 Nov 2012 22:15:55 -0700 |
Mike Pavone |
Finish mulu.w, muls.w and abcd parameter decoding
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| Sat, 03 Nov 2012 21:38:28 -0700 |
Mike Pavone |
Improve 68K instruction decoding. Add simple disassembler.
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| Mon, 29 Oct 2012 01:18:38 -0700 |
Mike Pavone |
Initial work on M68K instruction decoding
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