Mercurial > repos > blastem
log cpu_dsl.py @ 2048:ed9a6de28158 mame_interp
| age | author | description |
|---|---|---|
| Sat, 13 Jun 2020 00:37:22 -0700 | Michael Pavone | Somewhat buggy implementations of shift instructions in new 68K core |
| Thu, 23 Apr 2020 20:57:14 -0700 | Michael Pavone | Fix autogenerated temp variables in interrupt subroutine in CPU DSL |
| Sat, 21 Sep 2019 10:48:10 -0700 | Michael Pavone | Implement interrupts in call dispatch mode in CPU DSL |
| Thu, 18 Apr 2019 19:47:50 -0700 | Michael Pavone | WIP new 68K core using CPU DSL |
| Wed, 20 Feb 2019 00:34:52 -0800 | Michael Pavone | Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL |
| Tue, 19 Feb 2019 22:51:33 -0800 | Michael Pavone | Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core |
| Fri, 15 Feb 2019 23:58:34 -0800 | Michael Pavone | Basic support for string operands in CPU DSL |