Mercurial > repos > blastem
changeset 2056:27bbfcb7850a segacd
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Wed, 19 Jan 2022 00:08:01 -0800 |
| parents | c4d066d798c4 |
| children | 88deea42caf0 |
| files | segacd.c |
| diffstat | 1 files changed, 29 insertions(+), 8 deletions(-) [+] |
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--- a/segacd.c Tue Jan 18 23:54:02 2022 -0800 +++ b/segacd.c Wed Jan 19 00:08:01 2022 -0800 @@ -377,10 +377,22 @@ segacd_context *cd = m68k->system; uint32_t reg = (address & 0x1FF) >> 1; uint16_t value16; - if (address & 1) { - value16 = cd->gate_array[reg] & 0xFF00 | value; - } else { - value16 = cd->gate_array[reg] & 0xFF | (value << 8); + switch (address >> 1) + { + case GA_CDC_HOST_DATA: + case GA_CDC_DMA_ADDR: + case GA_STOP_WATCH: + case GA_COMM_FLAG: + case GA_CDD_FADER: + //these registers treat all writes as word-wide + value16 = value | (value << 8); + break; + default: + if (address & 1) { + value16 = cd->gate_array[reg] & 0xFF00 | value; + } else { + value16 = cd->gate_array[reg] & 0xFF | (value << 8); + } } return sub_gate_write16(address, vcontext, value16); } @@ -588,10 +600,19 @@ segacd_context *cd = gen->expansion; uint32_t reg = (address & 0x1FF) >> 1; uint16_t value16; - if (address & 1) { - value16 = cd->gate_array[reg] & 0xFF00 | value; - } else { - value16 = cd->gate_array[reg] & 0xFF | (value << 8); + switch (reg >> 1) + { + case GA_HINT_VECTOR: + case GA_COMM_FLAG: + //writes to these regs are always treated as word wide + value16 = value | (value << 8); + break; + default: + if (address & 1) { + value16 = cd->gate_array[reg] & 0xFF00 | value; + } else { + value16 = cd->gate_array[reg] & 0xFF | (value << 8); + } } return main_gate_write16(address, vcontext, value16); }