changeset 2671:e0935d5878c3

Fix some cycle timing issues in the new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sat, 08 Mar 2025 19:57:23 -0800
parents 9bcfdc1b56bd
children 6894a25ebfaa
files m68k.cpu
diffstat 1 files changed, 70 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/m68k.cpu	Sat Mar 08 18:56:57 2025 -0800
+++ b/m68k.cpu	Sat Mar 08 19:57:23 2025 -0800
@@ -461,6 +461,25 @@
 	invalid M 7 R 7
 	invalid Z 3
 	m68k_fetch_src_ea M R Z
+	if Z = 2
+		switch M
+		case 0
+			#dreg src
+			cycles 4
+		case 1
+			#areg src
+			cycles 4
+		case 7
+			if R = 4
+				#immediate
+				cycles 4
+			else
+				cycles 2
+			end
+		default
+			cycles 2
+		end
+	end
 	
 	add src dregs.D dregs.D Z
 	update_flags XNZVC
@@ -572,6 +591,12 @@
 	
 	m68k_fetch_dst_ea M R Z
 	switch M
+	case 0
+		if Z = 2
+			cycles 4
+		end
+		add src dst dst Z
+		update_flags XNZVC
 	case 1
 		cycles 4
 		add src dst dst 2
@@ -681,6 +706,25 @@
 	invalid M 7 R 7
 	invalid Z 3
 	m68k_fetch_src_ea M R Z
+	if Z = 2
+		switch M
+		case 0
+			#dreg src
+			cycles 4
+		case 1
+			#areg src
+			cycles 4
+		case 7
+			if R = 4
+				#immediate
+				cycles 4
+			else
+				cycles 2
+			end
+		default
+			cycles 2
+		end
+	end
 	
 	and src dregs.D dregs.D Z
 	update_flags NZV0C0
@@ -1218,6 +1262,25 @@
 	invalid M 7 R 7
 	invalid Z 3
 	m68k_fetch_src_ea M R Z
+	if Z = 2
+		switch M
+		case 0
+			#dreg src
+			cycles 4
+		case 1
+			#areg src
+			cycles 4
+		case 7
+			if R = 4
+				#immediate
+				cycles 4
+			else
+				cycles 2
+			end
+		default
+			cycles 2
+		end
+	end
 	
 	sub src dregs.D dregs.D Z
 	update_flags XNZVC
@@ -1329,7 +1392,14 @@
 	
 	m68k_fetch_dst_ea M R Z
 	switch M
+	case 0
+		if Z = 2
+			cycles 4
+		end
+		sub src dst dst Z
+		update_flags XNZVC
 	case 1
+		cycles 4
 		sub src dst dst 2
 	default
 		sub src dst dst Z