Mercurial > repos > blastem
log
| age | author | description |
|---|---|---|
| Tue, 17 Sep 2013 19:10:00 -0700 | Mike Pavone | Set VBLANK flag in status register when display is disabled |
| Tue, 17 Sep 2013 09:45:14 -0700 | Mike Pavone | Implement HV counter latch |
| Tue, 17 Sep 2013 00:42:49 -0700 | Mike Pavone | Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 |
| Tue, 17 Sep 2013 00:11:45 -0700 | Mike Pavone | Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. |
| Mon, 16 Sep 2013 09:44:22 -0700 | Mike Pavone | Partial fix for DMA copy |
| Sun, 15 Sep 2013 23:49:09 -0700 | Mike Pavone | Clear the low 2 bits of CD when a register is written to |
| Sun, 15 Sep 2013 23:40:18 -0700 | Mike Pavone | Don't allow register writes to regs above when in Mode 4 |