| Tue, 27 Nov 2012 22:50:09 -0800 |
Mike Pavone |
Add Makefile
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| Tue, 27 Nov 2012 22:43:32 -0800 |
Mike Pavone |
Make x86 generator generic with respect to operand size for immediate parameters.
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| Tue, 27 Nov 2012 09:28:13 -0800 |
Mike Pavone |
x86 code gen, initial work on translator
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| Thu, 15 Nov 2012 22:15:43 -0800 |
Mike Pavone |
Improve disassembly. FIx some decoding bugs.
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| Thu, 15 Nov 2012 00:52:53 -0800 |
Mike Pavone |
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
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| Wed, 14 Nov 2012 23:04:55 -0800 |
Mike Pavone |
Implement OR_DIV_SBCD group in decoder
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| Wed, 14 Nov 2012 09:24:40 -0800 |
Mike Pavone |
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
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| Tue, 13 Nov 2012 18:26:43 -0800 |
Mike Pavone |
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
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| Fri, 09 Nov 2012 22:01:26 -0800 |
Mike Pavone |
Finish bit/movep/immediate group except for 68020 instructions
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| Tue, 06 Nov 2012 02:07:45 -0800 |
Mike Pavone |
merge
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| Tue, 06 Nov 2012 01:57:36 -0800 |
Mike Pavone |
Add some logic analyzer captures, a Python script for analyzing said captures and a higher level analysis of the output
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| Tue, 06 Nov 2012 02:04:42 -0800 |
Mike Pavone |
More bit and immediate instructions
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| Sun, 04 Nov 2012 23:43:03 -0800 |
Mike Pavone |
Add support for some bit instructions and a few others in the same "category"
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| Sat, 03 Nov 2012 22:15:55 -0700 |
Mike Pavone |
Finish mulu.w, muls.w and abcd parameter decoding
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| Sat, 03 Nov 2012 21:38:28 -0700 |
Mike Pavone |
Improve 68K instruction decoding. Add simple disassembler.
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