| Wed, 19 Dec 2012 22:15:16 -0800 |
Mike Pavone |
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
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| Wed, 19 Dec 2012 21:25:39 -0800 |
Mike Pavone |
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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| Wed, 19 Dec 2012 20:53:59 -0800 |
Mike Pavone |
Add FPS counter to console output
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| Wed, 19 Dec 2012 20:53:45 -0800 |
Mike Pavone |
Print out large immediate values in hex rather than decimal form
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| Wed, 19 Dec 2012 20:23:59 -0800 |
Mike Pavone |
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
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| Tue, 18 Dec 2012 23:55:10 -0800 |
Mike Pavone |
Fix operand order for AND instructions
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| Tue, 18 Dec 2012 22:56:04 -0800 |
Mike Pavone |
ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
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| Tue, 18 Dec 2012 22:20:25 -0800 |
Mike Pavone |
Properly zero-init all VDP buffers. Comment out some debug printfs.
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| Tue, 18 Dec 2012 22:19:52 -0800 |
Mike Pavone |
Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
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| Tue, 18 Dec 2012 19:51:33 -0800 |
Mike Pavone |
Fix CRAM and possibly VSRAM writes
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| Tue, 18 Dec 2012 19:51:17 -0800 |
Mike Pavone |
Add palette debug to SDL renderer
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| Tue, 18 Dec 2012 02:16:42 -0800 |
Mike Pavone |
Get Flavio's color bar demo kind of sort of working
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| Sun, 16 Dec 2012 22:25:29 -0800 |
Mike Pavone |
Add preliminary support for JMP
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| Sun, 16 Dec 2012 21:57:52 -0800 |
Mike Pavone |
Implement CLR, minor refactor of register offset calculation in context struct
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| Sat, 15 Dec 2012 23:01:32 -0800 |
Mike Pavone |
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
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