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annotate simple_console.txt @ 46:51672bd41cdd

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Rework data segment setup to allow a stack segment and to add space for push and pop instructions
author Michael Pavone <pavone@retrodev.com>
date Tue, 30 Aug 2016 20:50:54 -0700
parents 6e7bfe83d2b0
children c44170825b16
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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1 Key:
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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2 1 = literal 1 bit
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3 0 = literal 0 bit
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4 O = opcode bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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5 D = destination register bit
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6 A = source A register bit
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7 B = source B register bit
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8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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9 DDDD AAAA BBBB OOOO
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10
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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11 0: ldim
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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12 D = destination reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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13 A and B form 8-bit immediate value
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14 1: ldimh
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15 D = destination reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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16 A and B form 8-bit immediate value
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17 2: ld8
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18 3: ld16
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19 4: str8
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20 5: str16
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21 6: add
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22 7: adc
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23 8: and
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24 9: or
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25 A: xor
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26 B: lsl
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27 C: lsr
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28 D: asr
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29 E: bcc
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30 F: single source
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31
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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32
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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33
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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34 DDDD AAAA OOOO 1111
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35
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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36 single source
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37
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38 0: mov
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39 1: neg
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40 2: not
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41 3: cmp
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42 4: call
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43 A = register containing pointer to function
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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44 D = register that will store PC value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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45 5: swap
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6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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46 6: longjmp
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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47 A = register containing pointer to function
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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48 D = register containing new code segment value
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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49 7: ini
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50 8: outi
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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51 9: addi
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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52 A: andi
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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53 B: ori
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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54 C: xori
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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55 D: ls[lr]i
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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56 MSB of AAAA determines direction
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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57 LS 3 bits determines magnitude
2
6204c81e2933 Revert changes to handling of immediate versions of bitwise instructions. Replace asri with cmpi.
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58 E: cmpi
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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59 F: single reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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60
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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61
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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62 DDDD OOOO 1111 1111
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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63
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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64 0: reti - return from interrupt, D = register to restore from uer
43
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65 1: trapi
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51672bd41cdd Rework data segment setup to allow a stack segment and to add space for push and pop instructions
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66 2: push
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67 3: pop
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68 4: getpch
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69 5: setpch
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70 6: getepc
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71 7: setepc
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72 8: getesr
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73 9: setesr
43
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74 A: getuer
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75 B: setuer
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76 C: getenum
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77 D: setenum
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78 E: getvbr
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79 F: setvbr
0
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80
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81
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82 Registers:
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83
46
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84 r0 - r11 : general purpose
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85 r12 : Data Banks - Holds the upper bytes used for data accesses (MSB = byte for lower half of memory space, LSB = byte for upper half of memory space)
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86 r13 : stack register
0
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87 r14 : PC
46
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88 r15 : status register, Stack MSB
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89 Layout: XSSS SSSS XXXN CZ10
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90 S = Stack most significant bits
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91 N = Negaitve flag
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92 C = Carry flag
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93 Z = Zero flag
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94 1 = Interrupt 1 enable
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95 0 = Interrupt 0 enable
0
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96
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
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97 Special Registers
46
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98 pch - PC High - Low byte stores current PC High value, Upper byte stores saved PC High value when entering an exception handler
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
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99 epc - Exception PC - Stores PC value to resume to when entering an exception handler
08b69e3f9f17 Fleshed out the video hardware design somewhat
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100 esr - Exception SR - same as above, but for SR
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101 eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer
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102 enum - Exception Number - holds the number of the most recent exception
46
51672bd41cdd Rework data segment setup to allow a stack segment and to add space for push and pop instructions
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103 vbr - Vector Base Register - Base address in page 0 of vector table
3
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104
0
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105 IO: Ports
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106
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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107 0: Controller 1
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108 1: Controller 2
27
351a0d0cce3b Updated spec to make the 3rd and 4th controller IO ports as reserved
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109 2: Reserved
351a0d0cce3b Updated spec to make the 3rd and 4th controller IO ports as reserved
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110 3: Reserved
0
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111
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112 4: Channel A Freq
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113 Load value for a 16-bit down-counter
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114 Polarity of output is switched on transition from 1 to 0
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115 Value is loaded on cycles where counter is 0
43
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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116 Special case value of 0 in this register forces polarity to positive, useful for PCM playback
0
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117 5: Channel B Freq
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118 6: Channel C Freq
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119 7: Channel D Freq
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120
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121 8: Channel A/B Vol
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122 9: Channel C/D Vol
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123
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124 A: Timer Freq
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125 B: "Serial" Debug Port
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126
43
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127 C: Framebuffer start offset : Read Vertical Position
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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128 D: Graphics mode : Read Horizontal Position
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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129 EDVP PSSS SSEE EEEF
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130 E = 0 display disabled, 1 display enabled
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131 D = 0 4 bpp, 1 8bpp
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132 F = 0 front buffer is lower 64K, 1 front buffer is upper 64K
6e7bfe83d2b0 Changed the design to vastly simplify the video hardware and support a 23-bit address space on the CPU
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133 P = palette select
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134 S = blanked lines at start of frame
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135 E = blanked lines at end of frame
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136 E: CRAM update port : Read Status
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137 1st write determines destination and length
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138 DDDD DDDD LLLL LLLL
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139 Next L writes are written to D and subsequent addresses
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140
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141 F: Reserved
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142
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143
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144 Video Hardware:
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145 128KB of VRAM organized into two 64KB linear framebuffers
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146 Pixels are 4bpp or 8bbp in chunky format
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147 256 words of 16-bit CRAM
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148 In 4bpp mode, P field of graphics mode selects one of 4, 16 color palettes
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149 S and E fields of mode allow hardware letter boxing, effectively increasing the length of vblank
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150 F field selects which 64KB framebuffer is used for the active display
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151 Active buffer is inaccessible to CPU, but CPU has free reign over inactive buffer
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152 H-Counter goes from 0-415 and then wraps back to zero
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153 V-Counter goes from 0-261 and then wraps back to zero
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154 V-Counter increments when H-Counter wraps
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155
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156 Memory Map
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157 23-bit address space
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158 $0 - $3FFFFF - ROM
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159 $400000 - $4FFFFF - 128K RAM, mirrored every 128KB
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160 $500000 - $6FFFFF - Reserved
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161 $700000 - $7FFFFF - 64KB VRAM back buffer, mirrored every 64KB
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162
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163 Banking/Segments:
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164 Code Segment: 64KB, used for instruction fetch and PC-relative load/stores
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165 Stack Segment: 64KB, used for push/pop and SP-relative load/stores
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166 Upper Data Segment: 32KB, used for load/stores to addresses in the upper half of the 16-bit address space
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167 Lower Data Segment: 32KB, used for load/stores to addresses in the lower half of the 16-bit address space
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168
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169 23-bit address generation details:
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170 Code segment
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171 r14 (aka PC) is used for the low 16 bits of the address and PCH is used for the upper 7 bits
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172 Stack Segment
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173 r13 (aka SP) is used for the low 16 bits of the address and the upper byte of SR is used for
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174 the upper 7-bits. Note that for a load/store that uses both PC and SP, the code segment is used
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175 Data segments
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176 The low 15-bits of the computed 16-bit address are used directly. The most significant bit
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177 selects a data segment and then the relevant byte of r12 is used for the upper 8 bits
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178 26.112 MHZ Clock
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179 Dot Clock Divider 4
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180 CPU Clock Divider 4 (assuming 1 cycle/instruction, 1 for 4 cycles/instruction)
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181 Audio Timer Divider 34
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182 Audio Output Divider 544
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183 Interrupt Timer Divider 32
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184
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185 Alternatively 13.056 Mhz clock and cut the dividers in half
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186
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187