Mercurial > repos > tabletprog
annotate modules/x86.tp @ 186:35d2cc193d99
Add string conversion inside array join so callers don't need to worry about doing string conversions themselves
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 26 Aug 2013 17:27:17 -0700 |
parents | 97f107b9e8d3 |
children | 4293c725394c |
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1 { |
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2 regnames <- #["rax" "rcx" "rdx" "rbx" "rsp" "rbp" "rsi" "rdi" "r8" "r9" "r10" "r11" "r12" "r13" "r14" "r15"] |
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3 uppernames <- #["ah" "ch" "dh" "bh"] |
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4 ireg <- :regnum { |
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5 #{ |
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6 num <- { regnum } |
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7 reg <- { regnum and 7u8} |
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8 string <- { regnames get: regnum } |
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9 rm <- :tail { reg or 0xC0u8 | tail } |
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10 validforSize? <- :size { true } |
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11 isInteger? <- { false } |
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12 register? <- { true } |
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13 label? <- { false } |
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14 upper? <- { true } |
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15 needsRex? <- { regnum >= 8u8 } |
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16 rexBitReg <- { |
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17 if: needsRex? { |
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18 4u8 |
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19 } else: { |
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20 0u8 |
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21 } |
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22 } |
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23 rexBitRM <- { |
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24 if: needsRex? { |
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25 1u8 |
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26 } else: { |
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27 0u8 |
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28 } |
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29 } |
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30 = <- :other { |
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31 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num) |
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32 } |
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33 } |
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34 } |
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35 |
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36 upper <- :regnum { |
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37 #{ |
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38 num <- { regnum } |
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39 reg <- { regnum } |
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40 string <- { uppernames get: regnum - 4 } |
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41 rm <- :tail { regnum or 0xC0u8 | tail } |
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42 validforSize? <- :size { |
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43 size = byte |
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44 } |
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45 isInteger? <- { false } |
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46 register? <- { true } |
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47 label? <- { false } |
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48 upper? <- { true } |
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49 needsRex? <- { false } |
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50 = <- :other { |
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51 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num) |
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52 } |
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53 } |
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54 } |
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55 fakesrc <- #{ |
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56 needsRex? <- { false } |
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57 rexBitReg <- { 0u8 } |
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58 rexBitRM <- { 0u8 } |
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59 } |
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60 size <- :s { |
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61 #{ |
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62 num <- { s } |
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63 = <- :other { |
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64 s = (other num) |
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65 } |
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66 > <- :other { |
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67 s > (other num) |
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68 } |
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69 >= <- :other { |
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70 s >= (other num) |
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71 } |
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72 < <- :other { |
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73 s < (other num) |
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74 } |
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75 <= <- :other { |
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76 s <= (other num) |
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77 } |
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78 needsRex? <- { s = 3 } |
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79 rexBit <- { |
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80 if: needsRex? { |
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81 0x08u8 |
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82 } else: { |
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83 0u8 |
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84 } |
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85 } |
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86 } |
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87 } |
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88 byte <- size: 0 |
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89 word <- size: 1 |
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90 dword <- size: 2 |
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91 qword <- size: 3 |
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92 |
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93 condition <- :num { |
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94 #{ |
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95 cc <- { num } |
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96 } |
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97 } |
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98 _o <- condition: 0u8 |
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99 _no <- condition: 1u8 |
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100 _c <- condition: 2u8 |
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101 _nc <- condition: 3u8 |
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102 _z <- condition: 4u8 |
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103 _nz <- condition: 5u8 |
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104 _be <- condition: 6u8 |
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105 _nbe <- condition: 7u8 |
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106 _s <- condition: 8u8 |
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107 _ns <- condition: 9u8 |
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108 _p <- condition: 10u8 |
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109 _np <- condition: 11u8 |
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110 _l <- condition: 12u8 |
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111 _nl <- condition: 13u8 |
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112 _le <- condition: 14u8 |
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113 _nle <- condition: 15u8 |
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114 |
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115 |
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116 size_bit <- :opcode size { |
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117 if: size = byte { |
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118 opcode |
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119 } else: { |
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120 opcode or 1u8 |
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121 } |
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122 } |
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123 opex <- :val { |
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124 #{ |
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125 reg <- { val } |
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126 string <- { "opex " . val} |
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127 } |
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128 } |
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129 |
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130 mod_rm:withTail <- :register regmem :end { |
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131 l <- regmem rm: end |
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132 (l value) or ( lshift: (register reg) by: 3u8) | (l tail) |
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133 } |
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134 |
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135 mod_rm <- :reg rm { |
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136 mod_rm: reg rm withTail: [] |
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137 } |
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138 |
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139 int_op:withTail <- :value size :tail { |
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140 if: size >= dword { |
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141 tail <- (uint8: (rshift: value by: 16u64)) | (uint8: (rshift: value by: 24u64)) | tail |
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142 } |
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143 if: size >= word { |
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144 tail <- (uint8: (rshift: value by: 8u64)) | tail |
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145 } |
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146 (uint8: value) | tail |
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147 } |
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148 int_op <- :value size { |
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149 int_op: value size withTail: [] |
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150 } |
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151 //used for mov instructions that support 64-bit immediate operands/offsets |
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152 int_op64 <- :value size { |
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153 tail <- [] |
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154 value <- uint64: value |
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155 if: size = qword { |
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156 tail <- (uint8: (rshift: value by: 32u64)) | (uint8: (rshift: value by: 40u64)) | (uint8: (rshift: value by: 48u64)) | (uint8: (rshift: value by: 56u64)) | tail |
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157 } |
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158 int_op: value size withTail: tail |
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159 } |
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160 |
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161 prefix:withInstruction <- :reg rm size :inst { |
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162 if: size = word { |
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163 inst <- 0x66u8 | inst |
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164 } |
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165 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) { |
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166 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM) |
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167 inst <- rex | inst |
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168 } |
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169 inst |
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170 } |
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171 |
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172 _rax <- ireg: 0u8 |
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173 _rcx <- ireg: 1u8 |
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174 _rdx <- ireg: 2u8 |
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175 _rbx <- ireg: 3u8 |
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176 _rsp <- ireg: 4u8 |
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177 _rbp <- ireg: 5u8 |
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178 _rsi <- ireg: 6u8 |
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179 _rdi <- ireg: 7u8 |
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180 _r8 <- ireg: 8u8 |
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181 _r9 <- ireg: 9u8 |
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182 _r10 <- ireg: 10u8 |
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183 _r11 <- ireg: 11u8 |
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184 _r12 <- ireg: 12u8 |
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185 _r13 <- ireg: 13u8 |
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186 _r14 <- ireg: 14u8 |
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187 _r15 <- ireg: 15u8 |
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188 _ah <- upper: 4u8 |
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189 _ch <- upper: 5u8 |
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190 _dh <- upper: 6u8 |
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191 _bh <- upper: 7u8 |
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192 |
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193 inst <- :ilist { |
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194 #{ |
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195 length <- { ilist length } |
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196 flattenTo:at <- :dest :idx { |
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197 ilist fold: idx with: :idx byte { |
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198 dest set: idx byte |
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199 idx + 1 |
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200 } |
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201 } |
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202 } |
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203 } |
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204 |
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205 op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex { |
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206 reg <- src |
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207 rm <- dst |
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208 base <- if: (src isInteger?) { |
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209 reg <- fakesrc |
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210 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size)) |
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211 } else: { |
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212 if: (src register?) { |
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213 (size_bit: normal size) | (mod_rm: src dst) |
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214 } else: { |
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215 reg <- dst |
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216 rm <- src |
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217 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src) |
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218 } |
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219 } |
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220 inst: (prefix: reg rm size withInstruction: base) |
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221 } |
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222 |
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223 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt { |
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224 reg <- src |
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225 rm <- dst |
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226 if: (src isInteger?) { |
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227 reg <- fakesrc |
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228 base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) { |
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229 byteExt | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)]) |
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230 } else: { |
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231 if: dst = _rax { |
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232 (size_bit: immedRax size) | (int_op: src size) |
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233 } else: { |
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234 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size)) |
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235 } |
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236 } |
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237 inst: (prefix: reg rm size withInstruction: base) |
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238 } else: { |
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239 op: src dst size withCode: normal withImmed: immed withOpEx: myopex |
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240 } |
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241 } |
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242 |
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243 _jmprel <- :op jmpDest { |
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244 } |
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245 |
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246 #{ |
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247 rax <- { _rax } |
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248 rcx <- { _rcx } |
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249 rdx <- { _rdx } |
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250 rbx <- { _rbx } |
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251 rsp <- { _rsp } |
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252 rbp <- { _rbp } |
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253 rsi <- { _rsi } |
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254 rdi <- { _rdi } |
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255 r8 <- { _r8 } |
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256 r9 <- { _r9 } |
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257 r10 <- { _r10 } |
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258 r11 <- { _r11 } |
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259 r12 <- { _r12 } |
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260 r13 <- { _r13 } |
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261 r14 <- { _r14 } |
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262 r15 <- { _r15 } |
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263 ah <- { _ah } |
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264 ch <- { _ch } |
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265 dh <- { _dh } |
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266 bh <- { _bh } |
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267 |
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268 b <- { byte } |
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269 w <- { word } |
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270 d <- { dword } |
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271 q <- { qword } |
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272 |
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273 o <- { _o } |
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274 no <- { _no } |
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275 c <- { _c } |
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276 nc <- { _nc } |
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277 ae <- { _nc } |
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278 z <- { _z } |
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279 e <- { _z } |
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280 nz <- { _nz } |
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281 ne <- { _nz } |
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282 be <- { _be } |
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283 nbe <- { _nbe } |
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284 a <- { _nbe } |
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285 s <- { _s } |
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286 ns <- { _ns } |
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287 p <- { _p } |
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288 pe <- { _p } |
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289 np <- { _np } |
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290 po <- { _np } |
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291 l <- { _l } |
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292 nl <- { _nl } |
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293 ge <- { _nl } |
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294 le <- { _le } |
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295 nle <- { _nle } |
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296 g <- { _nle } |
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297 |
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298 add <- :src dst size { |
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299 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8 |
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300 } |
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301 |
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302 sub <- :src dst size { |
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303 op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8 |
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304 } |
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305 |
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306 mov <- :src dst size { |
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307 rm <- dst |
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308 if: (src isInteger?) && (dst register?) { |
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309 opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 } |
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310 base <- opval or (dst reg) | (int_op64: src size) |
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311 inst: (prefix: fakesrc rm size withInstruction: base) |
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312 } else: { |
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313 op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8 |
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314 } |
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315 } |
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316 |
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317 ret <- { inst: [ 0xC3u8 ] } |
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318 |
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319 label <- { |
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320 _offset <- -1 |
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321 _forwardRefs <- #[] |
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322 #{ |
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323 length <- { 0 } |
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324 hasOffset? <- { _offset >= 0 } |
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325 offset <- { _offset } |
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326 register? <- { false } |
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327 label? <- { true } |
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328 flattenTo:at <- :dest :idx { |
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329 if: (not: hasOffset?) { |
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330 _offset <- idx |
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331 foreach: _forwardRefs :idx fun { |
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332 fun: _offset |
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333 } |
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334 _forwardRefs <- #[] |
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335 } |
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336 idx |
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337 } |
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338 withOffset:else <- :fun :elsefun { |
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339 if: hasOffset? { |
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340 fun: _offset |
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341 } else: { |
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342 _forwardRefs append: fun |
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343 elsefun: |
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344 } |
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345 } |
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346 } |
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347 } |
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348 |
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349 jmp <- :jmpDest { |
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350 if: (jmpDest label?) { |
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351 _size <- -1 |
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352 #{ |
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353 length <- { if: _size < 0 { 5 } else: { _size } } |
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354 flattenTo:at <- :dest :idx { |
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355 jmpDest withOffset: :off { |
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356 if: _size < 0 { |
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357 rel <- off - (idx + 2) |
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358 if: rel < 128 && rel >= -128 { |
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359 _size <- 2 |
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360 } else: { |
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361 rel <- rel - 2 |
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362 if: rel < 32768 && rel >= -32768 { |
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363 _size <- 4 |
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364 } else: { |
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365 _size <- 5 |
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366 } |
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367 } |
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368 } |
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369 rel <- off - (idx + _size) |
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370 if: _size = 2 { |
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371 dest set: idx 0xEBu8 |
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372 dest set: (idx + 1) (uint8: rel) |
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373 } else: { |
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374 if: _size = 4 { |
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375 dest set: idx 0x66u8 |
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376 dest set: (idx + 1) 0xE9u8 |
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377 dest set: (idx + 2) (uint8: rel) |
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378 dest set: (idx + 3) (uint8: (rshift: rel by: 8)) |
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379 } else: { |
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380 dest set: idx 0xE9u8 |
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381 dest set: (idx + 1) (uint8: rel) |
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382 dest set: (idx + 2) (uint8: (rshift: rel by: 8)) |
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383 dest set: (idx + 3) (uint8: (rshift: rel by: 16)) |
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384 dest set: (idx + 4) (uint8: (rshift: rel by: 24)) |
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385 } |
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386 } |
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387 } else: { |
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388 _size <- 5 |
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389 } |
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390 idx + _size |
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391 } |
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392 } |
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393 } else: { |
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394 inst: 0xFFu8 | (mod_rm: (opex: 5u8) jmpDest) |
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395 } |
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396 } |
175
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397 |
183
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398 jcc <- :cond jmpDest { |
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399 _size <- -1 |
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400 #{ |
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401 length <- { if: _size < 0 { 5 } else: { _size } } |
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402 flattenTo:at <- :dest :idx { |
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403 jmpDest withOffset: :off { |
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404 if: _size < 0 { |
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405 rel <- off - (idx + 2) |
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406 if: rel < 128 && rel >= -128 { |
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407 _size <- 2 |
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408 } else: { |
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409 _size <- 6 |
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410 } |
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411 } |
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412 rel <- off - (idx + _size) |
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413 if: _size = 2 { |
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414 dest set: idx 0x70u8 or (cond cc) |
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415 dest set: (idx + 1) (uint8: rel) |
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416 } else: { |
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417 dest set: idx 0x0Fu8 |
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418 dest set: (idx + 1) 0x80u8 or (cond cc) |
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419 dest set: (idx + 2) (uint8: rel) |
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420 dest set: (idx + 3) (uint8: (rshift: rel by: 8)) |
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421 dest set: (idx + 4) (uint8: (rshift: rel by: 16)) |
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422 dest set: (idx + 5) (uint8: (rshift: rel by: 24)) |
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423 } |
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424 } else: { |
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425 _size <- 6 |
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426 } |
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427 idx + _size |
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428 } |
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429 } |
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430 } |
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431 |
181
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432 call <- :callDest { |
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433 if: (callDest label?) { |
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434 #{ |
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435 length <- { 5 } |
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436 flattenTo:at <- :dest :idx { |
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437 dest set: idx 0xE8u8 |
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438 callDest withOffset: :off { |
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439 rel <- off - (idx + 5) |
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440 dest set: (idx + 1) (uint8: rel) |
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441 dest set: (idx + 2) (uint8: (rshift: rel by: 8)) |
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442 dest set: (idx + 3) (uint8: (rshift: rel by: 16)) |
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443 dest set: (idx + 4) (uint8: (rshift: rel by: 24)) |
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444 } else: { |
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445 } |
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446 idx + 5 |
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447 } |
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448 } |
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449 } else: { |
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450 inst: 0xFFu8 | (mod_rm: (opex: 2u8) callDest) |
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451 } |
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452 } |
174
8b5829372ad1
Initial work on x86 instruction encoding module
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|
453 |
183
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454 push <- :src { |
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455 if: (src isInteger?) { |
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456 if: src < 128 && src > -128 { |
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457 inst: 0x6Au8 | (uint8: src) |
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458 } else: { |
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459 inst: 0x68u8 | (uint8: src) | (uint8: (rshift: src by: 8)) | (uint8: (rshift: src by: 16)) | (uint8: (rshift: src by: 24)) |
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460 } |
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461 } else: { |
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462 base <- if: (src register?) { |
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463 [0x50u8 or (src reg)] |
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464 } else: { |
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465 0xFFu8 | (mod_rm: (opex: 6u8) src) |
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466 } |
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467 inst: (prefix: fakesrc src d withInstruction: base) |
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468 } |
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469 } |
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470 |
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471 pop <- :dst { |
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472 base <- if: (dst register?) { |
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473 [0x58u8 or (dst reg)] |
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474 } else: { |
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475 0x8Fu8 | (mod_rm: (opex: 0u8) dst) |
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476 } |
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477 inst: (prefix: fakesrc dst d withInstruction: base) |
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478 } |
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479 |
174
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Initial work on x86 instruction encoding module
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|
480 main <- { |
183
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481 fib <- label: |
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482 notbase <- label: |
179
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A bunch of fixes in x86 instruction encoding
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483 prog <- #[ |
183
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484 fib |
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485 sub: 2 rdi q |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
486 jcc: ge notbase |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
487 mov: 1 rax q |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
488 ret: |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
489 |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
490 notbase |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
491 push: rdi |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
492 call: fib |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
493 pop: rdi |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
494 push: rax |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
495 add: 1 rdi q |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
496 call: fib |
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
497 pop: rdi |
179
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
498 add: rdi rax q |
181
f188723c15b4
Add call instruction to x86 module
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
499 ret: |
179
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
500 ] |
180
270d31c6c4cd
Add support for jmps and labels in x86 module
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
501 |
179
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
502 ba <- bytearray executableFromBytes: prog |
183
97f107b9e8d3
Fix a few bugs in the x86 module and add jcc, push and pop instructions
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
503 res <- ba runWithArg: 30u64 |
179
75aca5f87969
A bunch of fixes in x86 instruction encoding
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
504 print: (string: res) . "\n" |
174
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 0 |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 } |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 } |
8b5829372ad1
Initial work on x86 instruction encoding module
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 } |