Mercurial > repos > blastem

annotate gen_x86.c @ 226:28a6697e847b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Implement CHK instruction (not fully tested).
author Mike Pavone <pavone@retrodev.com>
date Sun, 21 Apr 2013 13:00:34 -0700
parents c82f65a87a53
children d9bf8e61c33c
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2 #include "68kinst.h"
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 #include <stddef.h>
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 #include <stdio.h>
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #define REX_RM_FIELD 0x1
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 #define REX_SIB_FIELD 0x2
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 #define REX_REG_FIELD 0x4
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 #define REX_QUAD 0x8
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 #define OP_ADD 0x00
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 #define OP_OR 0x08
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 #define PRE_2BYTE 0x0F
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 #define OP_ADC 0x10
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 #define OP_SBB 0x18
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 #define OP_AND 0x20
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 #define OP_SUB 0x28
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 #define OP_XOR 0x30
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 #define OP_CMP 0x38
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
20 #define PRE_REX 0x40
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21 #define OP_PUSH 0x50
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 #define OP_POP 0x58
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
23 #define OP_MOVSXD 0x63
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 #define PRE_SIZE 0x66
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 #define OP_JCC 0x70
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 #define OP_IMMED_ARITH 0x80
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 #define OP_MOV 0x88
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
28 #define OP_CDQ 0x99
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 #define OP_PUSHF 0x9C
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 #define OP_POPF 0x9D
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 #define OP_MOV_I8R 0xB0
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 #define OP_MOV_IR 0xB8
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
33 #define OP_SHIFTROT_IR 0xC0
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 #define OP_RETN 0xC3
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
35 #define OP_MOV_IEA 0xC6
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
36 #define OP_SHIFTROT_1 0xD0
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
37 #define OP_SHIFTROT_CL 0xD2
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
38 #define OP_LOOP 0xE2
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
39 #define OP_CALL 0xE8
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
40 #define OP_JMP 0xE9
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
41 #define OP_JMP_BYTE 0xEB
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
42 #define OP_NOT_NEG 0xF6
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
43 #define OP_SINGLE_EA 0xFF
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 #define OP2_JCC 0x80
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 #define OP2_SETCC 0x90
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
47 #define OP2_BT 0xA3
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
48 #define OP2_BTS 0xAB
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
49 #define OP2_IMUL 0xAF
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
50 #define OP2_BTR 0xB3
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
51 #define OP2_BTX_I 0xBA
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
52 #define OP2_BTC 0xBB
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
53 #define OP2_MOVSX 0xBE
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
54 #define OP2_MOVZX 0xB6
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 #define OP_EX_ADDI 0x0
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 #define OP_EX_ORI 0x1
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 #define OP_EX_ADCI 0x2
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59 #define OP_EX_SBBI 0x3
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
60 #define OP_EX_ANDI 0x4
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
61 #define OP_EX_SUBI 0x5
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
62 #define OP_EX_XORI 0x6
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
63 #define OP_EX_CMPI 0x7
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
64
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
65 #define OP_EX_ROL 0x0
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
66 #define OP_EX_ROR 0x1
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
67 #define OP_EX_RCL 0x2
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
68 #define OP_EX_RCR 0x3
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
69 #define OP_EX_SHL 0x4
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
70 #define OP_EX_SHR 0x5
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
71 #define OP_EX_SAL 0x6 //identical to SHL
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
72 #define OP_EX_SAR 0x7
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
73
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
74 #define OP_EX_BT 0x4
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
75 #define OP_EX_BTS 0x5
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
76 #define OP_EX_BTR 0x6
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
77 #define OP_EX_BTC 0x7
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
78
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
79 #define OP_EX_TEST_I 0x0
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
80 #define OP_EX_NOT 0x2
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
81 #define OP_EX_NEG 0x3
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
82 #define OP_EX_MUL 0x4
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
83 #define OP_EX_IMUL 0x5
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
84 #define OP_EX_DIV 0x6
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
85 #define OP_EX_IDIV 0x7
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
86
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
87 #define OP_EX_INC 0x0
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
88 #define OP_EX_DEC 0x1
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
89 #define OP_EX_CALL_EA 0x2
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
90 #define OP_EX_JMP_EA 0x4
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
91 #define OP_EX_PUSH_EA 0x6
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
92
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
93 #define BIT_IMMED_RAX 0x4
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
94 #define BIT_DIR 0x2
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
95 #define BIT_SIZE 0x1
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
96
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
97
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
98 enum {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
99 X86_RAX = 0,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
100 X86_RCX,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 X86_RDX,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
102 X86_RBX,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
103 X86_RSP,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
104 X86_RBP,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
105 X86_RSI,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
106 X86_RDI,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
107 X86_AH=4,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
108 X86_CH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
109 X86_DH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
110 X86_BH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
111 X86_R8=0,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
112 X86_R9,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
113 X86_R10,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
114 X86_R11,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
115 X86_R12,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
116 X86_R13,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
117 X86_R14,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
118 X86_R15
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
119 } x86_regs_enc;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
120
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
121 uint8_t * x86_rr_sizedir(uint8_t * out, uint16_t opcode, uint8_t src, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
122 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
123 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
124 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128 if (size == SZ_B && dst >= RSP && dst <= RDI) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
129 opcode |= BIT_DIR;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 tmp = dst;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
131 dst = src;
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
132 src = tmp;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
133 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
134 if (size == SZ_Q || src >= R8 || dst >= R8 || (size == SZ_B && src >= RSP && src <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
135 *out = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
136 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
137 *out |= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
139 if (src >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140 *out |= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
141 src -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
142 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
143 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
144 *out |= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
145 dst -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
146 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
147 out++;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
148 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
149 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
150 if (src >= AH && src <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
151 src -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
152 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
153 if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
154 dst -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
155 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156 } else {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
157 opcode |= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
158 }
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
159 if (opcode >= 0x100) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
160 *(out++) = opcode >> 8;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
161 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
162 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
163 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
164 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165 *(out++) = MODE_REG_DIRECT | dst | (src << 3);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
167 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
168
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
169 uint8_t * x86_rrdisp8_sizedir(uint8_t * out, uint16_t opcode, uint8_t reg, uint8_t base, int8_t disp, uint8_t size, uint8_t dir)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
170 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
172 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
174 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 if (size == SZ_Q || reg >= R8 || base >= R8 || (size == SZ_B && reg >= RSP && reg <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 *out = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 *out |= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 *out |= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 reg -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
184 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 if (base >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 *out |= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
187 base -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
188 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189 out++;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
191 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 if (reg >= AH && reg <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 reg -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
195 } else {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 opcode |= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 }
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
198 opcode |= dir;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
199 if (opcode >= 0x100) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
200 *(out++) = opcode >> 8;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
201 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
202 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
203 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
204 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205 *(out++) = MODE_REG_DISPLACE8 | base | (reg << 3);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
206 if (base == RSP) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
207 //add SIB byte, with no index and RSP as base
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
208 *(out++) = (RSP << 3) | RSP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
209 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 uint8_t * x86_rrind_sizedir(uint8_t * out, uint8_t opcode, uint8_t reg, uint8_t base, uint8_t size, uint8_t dir)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
218 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
220 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 if (size == SZ_Q || reg >= R8 || base >= R8 || (size == SZ_B && reg >= RSP && reg <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
222 *out = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 *out |= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
227 *out |= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 reg -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
229 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
230 if (base >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 *out |= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232 base -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234 out++;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 if (reg >= AH && reg <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 reg -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
240 } else {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 opcode |= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 *(out++) = opcode | dir;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 *(out++) = MODE_REG_INDIRECT | base | (reg << 3);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
245 if (base == RSP) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
246 //add SIB byte, with no index and RSP as base
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
247 *(out++) = (RSP << 3) | RSP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
248 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
252 uint8_t * x86_r_size(uint8_t * out, uint8_t opcode, uint8_t opex, uint8_t dst, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
253 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
254 uint8_t tmp;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
255 if (size == SZ_W) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
256 *(out++) = PRE_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
257 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
258 if (size == SZ_Q || dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
259 *out = PRE_REX;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
260 if (size == SZ_Q) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
261 *out |= REX_QUAD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
262 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
263 if (dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
264 *out |= REX_RM_FIELD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
265 dst -= (R8 - X86_R8);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
266 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
267 out++;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
268 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
269 if (size == SZ_B) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
270 if (dst >= AH && dst <= BH) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
271 dst -= (AH-X86_AH);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
272 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
273 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
274 opcode |= BIT_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
275 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
276 *(out++) = opcode;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
277 *(out++) = MODE_REG_DIRECT | dst | (opex << 3);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
278 return out;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
279 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
280
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
281 uint8_t * x86_rdisp8_size(uint8_t * out, uint8_t opcode, uint8_t opex, uint8_t dst, int8_t disp, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
282 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
283 uint8_t tmp;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
284 if (size == SZ_W) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
285 *(out++) = PRE_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
286 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
287 if (size == SZ_Q || dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
288 *out = PRE_REX;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
289 if (size == SZ_Q) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
290 *out |= REX_QUAD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
291 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
292 if (dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
293 *out |= REX_RM_FIELD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
294 dst -= (R8 - X86_R8);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
295 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
296 out++;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
297 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
298 if (size != SZ_B) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
299 opcode |= BIT_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
300 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
301 *(out++) = opcode;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
302 *(out++) = MODE_REG_DISPLACE8 | dst | (opex << 3);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
303 *(out++) = disp;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
304 return out;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
305 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
306
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
307 uint8_t * x86_ir(uint8_t * out, uint8_t opcode, uint8_t op_ex, uint8_t al_opcode, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
309 uint8_t sign_extend = 0;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
310 if ((size == SZ_D || size == SZ_Q) && val <= 0x7F && val >= -0x80) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
311 sign_extend = 1;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
312 opcode |= BIT_DIR;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
313 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
314 if (size == SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
315 *(out++) = PRE_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
316 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
317 if (dst == RAX && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
318 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
319 al_opcode |= BIT_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
320 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
321 *out = PRE_REX | REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
322 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
323 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 *(out++) = al_opcode | BIT_IMMED_RAX;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325 } else {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
326 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
327 *out = PRE_REX;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
328 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
329 *out |= REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
330 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
331 if (dst >= R8) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
332 *out |= REX_RM_FIELD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
333 dst -= (R8 - X86_R8);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
334 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
335 out++;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
336 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338 dst -= (AH-X86_AH);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
339 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
340 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
341 opcode |= BIT_SIZE;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 *(out++) = opcode;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 *(out++) = MODE_REG_DIRECT | dst | (op_ex << 3);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 *(out++) = val;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
347 if (size != SZ_B && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
348 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
349 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
350 if (size != SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
351 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
352 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
353 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
354 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
355 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
356 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
357 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
358 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
359
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
360 uint8_t * x86_irdisp8(uint8_t * out, uint8_t opcode, uint8_t op_ex, int32_t val, uint8_t dst, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
361 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
362 uint8_t sign_extend = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
363 if ((size == SZ_D || size == SZ_Q) && val <= 0x7F && val >= -0x80) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
364 sign_extend = 1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
365 opcode |= BIT_DIR;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
366 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
367 if (size == SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
368 *(out++) = PRE_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
369 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
370
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
371 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
372 *out = PRE_REX;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
373 if (size == SZ_Q) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
374 *out |= REX_QUAD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
375 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
376 if (dst >= R8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
377 *out |= REX_RM_FIELD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
378 dst -= (R8 - X86_R8);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
379 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
380 out++;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
381 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
382 if (size != SZ_B) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
383 opcode |= BIT_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
384 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
385 *(out++) = opcode;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
386 *(out++) = MODE_REG_DISPLACE8 | dst | (op_ex << 3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
387 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
388 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
389 if (size != SZ_B && !sign_extend) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
390 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
391 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
392 if (size != SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
393 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
394 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
395 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
396 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
397 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
398 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
399 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
400 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
401
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
403 uint8_t * x86_shiftrot_ir(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
404 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
405 if (size == SZ_W) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
406 *(out++) = PRE_SIZE;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
407 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
408 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
409 *out = PRE_REX;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
410 if (size == SZ_Q) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
411 *out |= REX_QUAD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
412 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
413 if (dst >= R8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
414 *out |= REX_RM_FIELD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
415 dst -= (R8 - X86_R8);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
416 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
417 out++;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
418 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
419 if (dst >= AH && dst <= BH) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
420 dst -= (AH-X86_AH);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
421 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
422
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
423 *(out++) = (val == 1 ? OP_SHIFTROT_1: OP_SHIFTROT_IR) | (size == SZ_B ? 0 : BIT_SIZE);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
424 *(out++) = MODE_REG_DIRECT | dst | (op_ex << 3);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
425 if (val != 1) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
426 *(out++) = val;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
427 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
428 return out;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
429 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
430
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
431 uint8_t * x86_shiftrot_irdisp8(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
432 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
433 if (size == SZ_W) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
434 *(out++) = PRE_SIZE;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
435 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
436 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
437 *out = PRE_REX;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
438 if (size == SZ_Q) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
439 *out |= REX_QUAD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
440 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
441 if (dst >= R8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
442 *out |= REX_RM_FIELD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
443 dst -= (R8 - X86_R8);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
444 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
445 out++;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
446 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
447 if (dst >= AH && dst <= BH) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
448 dst -= (AH-X86_AH);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
449 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
450
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
451 *(out++) = (val == 1 ? OP_SHIFTROT_1: OP_SHIFTROT_IR) | (size == SZ_B ? 0 : BIT_SIZE);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
452 *(out++) = MODE_REG_DISPLACE8 | dst | (op_ex << 3);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
453 *(out++) = disp;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
454 if (val != 1) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
455 *(out++) = val;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
456 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
457 return out;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
458 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
459
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
460 uint8_t * x86_shiftrot_clr(uint8_t * out, uint8_t op_ex, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
461 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
462 if (size == SZ_W) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
463 *(out++) = PRE_SIZE;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
464 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
465 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
466 *out = PRE_REX;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
467 if (size == SZ_Q) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
468 *out |= REX_QUAD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
469 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
470 if (dst >= R8) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
471 *out |= REX_RM_FIELD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
472 dst -= (R8 - X86_R8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
473 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
474 out++;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
475 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
476 if (dst >= AH && dst <= BH) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
477 dst -= (AH-X86_AH);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
478 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
479
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
480 *(out++) = OP_SHIFTROT_CL | (size == SZ_B ? 0 : BIT_SIZE);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
481 *(out++) = MODE_REG_DIRECT | dst | (op_ex << 3);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
482 return out;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
483 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
484
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
485 uint8_t * x86_shiftrot_clrdisp8(uint8_t * out, uint8_t op_ex, uint8_t dst, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
486 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
487 if (size == SZ_W) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
488 *(out++) = PRE_SIZE;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
489 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
490 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
491 *out = PRE_REX;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
492 if (size == SZ_Q) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
493 *out |= REX_QUAD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
494 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
495 if (dst >= R8) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
496 *out |= REX_RM_FIELD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
497 dst -= (R8 - X86_R8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
498 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
499 out++;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
500 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
501 if (dst >= AH && dst <= BH) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
502 dst -= (AH-X86_AH);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
503 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
504
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
505 *(out++) = OP_SHIFTROT_CL | (size == SZ_B ? 0 : BIT_SIZE);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
506 *(out++) = MODE_REG_DISPLACE8 | dst | (op_ex << 3);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
507 *(out++) = disp;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
508 return out;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
509 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
510
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
511 uint8_t * rol_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
512 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
513 return x86_shiftrot_ir(out, OP_EX_ROL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
514 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
515
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
516 uint8_t * ror_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
517 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
518 return x86_shiftrot_ir(out, OP_EX_ROR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
519 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
520
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
521 uint8_t * rcl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
522 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
523 return x86_shiftrot_ir(out, OP_EX_RCL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
524 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
525
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
526 uint8_t * rcr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
527 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
528 return x86_shiftrot_ir(out, OP_EX_RCR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
529 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
530
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
531 uint8_t * shl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
532 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
533 return x86_shiftrot_ir(out, OP_EX_SHL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
534 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
535
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
536 uint8_t * shr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
537 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
538 return x86_shiftrot_ir(out, OP_EX_SHR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
539 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
540
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
541 uint8_t * sar_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
542 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
543 return x86_shiftrot_ir(out, OP_EX_SAR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
544 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
545
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
546 uint8_t * rol_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
547 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
548 return x86_shiftrot_irdisp8(out, OP_EX_ROL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
549 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
550
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
551 uint8_t * ror_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
552 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
553 return x86_shiftrot_irdisp8(out, OP_EX_ROR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
554 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
555
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
556 uint8_t * rcl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
557 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
558 return x86_shiftrot_irdisp8(out, OP_EX_RCL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
559 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
560
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
561 uint8_t * rcr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
562 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
563 return x86_shiftrot_irdisp8(out, OP_EX_RCR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
564 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
565
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
566 uint8_t * shl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
567 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
568 return x86_shiftrot_irdisp8(out, OP_EX_SHL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
569 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
570
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
571 uint8_t * shr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
572 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
573 return x86_shiftrot_irdisp8(out, OP_EX_SHR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
574 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
575
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
576 uint8_t * sar_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
577 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
578 return x86_shiftrot_irdisp8(out, OP_EX_SAR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
579 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
580
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
581 uint8_t * rol_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
582 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
583 return x86_shiftrot_clr(out, OP_EX_ROL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
584 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
585
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
586 uint8_t * ror_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
587 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
588 return x86_shiftrot_clr(out, OP_EX_ROR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
589 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
590
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
591 uint8_t * rcl_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
592 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
593 return x86_shiftrot_clr(out, OP_EX_RCL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
594 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
595
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
596 uint8_t * rcr_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
597 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
598 return x86_shiftrot_clr(out, OP_EX_RCR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
599 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
600
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
601 uint8_t * shl_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
602 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
603 return x86_shiftrot_clr(out, OP_EX_SHL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
604 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
605
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
606 uint8_t * shr_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
607 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
608 return x86_shiftrot_clr(out, OP_EX_SHR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
609 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
610
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
611 uint8_t * sar_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
612 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
613 return x86_shiftrot_clr(out, OP_EX_SAR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
614 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
615
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
616 uint8_t * rol_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
617 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
618 return x86_shiftrot_clrdisp8(out, OP_EX_ROL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
619 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
620
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
621 uint8_t * ror_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
622 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
623 return x86_shiftrot_clrdisp8(out, OP_EX_ROR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
624 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
625
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
626 uint8_t * rcl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
627 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
628 return x86_shiftrot_clrdisp8(out, OP_EX_RCL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
629 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
630
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
631 uint8_t * rcr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
632 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
633 return x86_shiftrot_clrdisp8(out, OP_EX_RCR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
634 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
635
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
636 uint8_t * shl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
637 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
638 return x86_shiftrot_clrdisp8(out, OP_EX_SHL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
639 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
640
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
641 uint8_t * shr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
642 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
643 return x86_shiftrot_clrdisp8(out, OP_EX_SHR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
644 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
645
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
646 uint8_t * sar_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
647 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
648 return x86_shiftrot_clrdisp8(out, OP_EX_SAR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
649 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
650
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
651 uint8_t * add_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
652 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
653 return x86_rr_sizedir(out, OP_ADD, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
654 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
655
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
656 uint8_t * add_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
657 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
658 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ADDI, OP_ADD, val, dst, size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
659 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
660
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
661 uint8_t * add_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
662 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
663 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ADDI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
664 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
665
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
666 uint8_t * add_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
667 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
668 return x86_rrdisp8_sizedir(out, OP_ADD, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
669 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
670
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
671 uint8_t * add_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
672 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
673 return x86_rrdisp8_sizedir(out, OP_ADD, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
674 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
675
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
676 uint8_t * adc_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
677 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
678 return x86_rr_sizedir(out, OP_ADC, src, dst, size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
679 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
680
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
681 uint8_t * adc_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
682 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
683 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ADCI, OP_ADC, val, dst, size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
684 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
685
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
686 uint8_t * adc_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
687 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
688 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ADCI, val, dst_base, disp, size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
689 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
690
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
691 uint8_t * adc_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
692 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
693 return x86_rrdisp8_sizedir(out, OP_ADC, src, dst_base, disp, size, 0);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
694 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
695
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
696 uint8_t * adc_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
697 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
698 return x86_rrdisp8_sizedir(out, OP_ADC, dst, src_base, disp, size, BIT_DIR);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
699 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
700
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
701 uint8_t * or_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
702 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
703 return x86_rr_sizedir(out, OP_OR, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
704 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
705 uint8_t * or_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
706 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
707 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ORI, OP_OR, val, dst, size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
708 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
709
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
710 uint8_t * or_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
711 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
712 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ORI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
713 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
714
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
715 uint8_t * or_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
716 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
717 return x86_rrdisp8_sizedir(out, OP_OR, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
718 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
719
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
720 uint8_t * or_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
721 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
722 return x86_rrdisp8_sizedir(out, OP_OR, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
723 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
724
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
725 uint8_t * and_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
726 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
727 return x86_rr_sizedir(out, OP_AND, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
728 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
729
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
730 uint8_t * and_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
731 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
732 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ANDI, OP_AND, val, dst, size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
733 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
734
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
735 uint8_t * and_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
736 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
737 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ANDI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
738 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
739
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
740 uint8_t * and_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
741 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
742 return x86_rrdisp8_sizedir(out, OP_AND, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
743 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
744
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
745 uint8_t * and_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
746 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
747 return x86_rrdisp8_sizedir(out, OP_AND, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
748 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
749
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
750 uint8_t * xor_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
751 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
752 return x86_rr_sizedir(out, OP_XOR, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
753 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
754
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
755 uint8_t * xor_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
756 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
757 return x86_ir(out, OP_IMMED_ARITH, OP_EX_XORI, OP_XOR, val, dst, size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
758 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
759
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
760 uint8_t * xor_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
761 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
762 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_XORI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
763 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
764
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
765 uint8_t * xor_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
766 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
767 return x86_rrdisp8_sizedir(out, OP_XOR, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
768 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
769
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
770 uint8_t * xor_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
771 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
772 return x86_rrdisp8_sizedir(out, OP_XOR, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
773 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
774
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
775 uint8_t * sub_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
776 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
777 return x86_rr_sizedir(out, OP_SUB, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
778 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
779
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
780 uint8_t * sub_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
781 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
782 return x86_ir(out, OP_IMMED_ARITH, OP_EX_SUBI, OP_SUB, val, dst, size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
783 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
784
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
785 uint8_t * sub_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
786 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
787 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_SUBI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
788 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
789
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
790 uint8_t * sub_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
791 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
792 return x86_rrdisp8_sizedir(out, OP_SUB, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
793 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
794
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
795 uint8_t * sub_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
796 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
797 return x86_rrdisp8_sizedir(out, OP_SUB, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
798 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
799
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
800 uint8_t * sbb_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
801 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
802 return x86_rr_sizedir(out, OP_SBB, src, dst, size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
803 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
804
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
805 uint8_t * sbb_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
806 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
807 return x86_ir(out, OP_IMMED_ARITH, OP_EX_SBBI, OP_SBB, val, dst, size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
808 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
809
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
810 uint8_t * sbb_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
811 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
812 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_SBBI, val, dst_base, disp, size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
813 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
814
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
815 uint8_t * sbb_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
816 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
817 return x86_rrdisp8_sizedir(out, OP_SBB, src, dst_base, disp, size, 0);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
818 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
819
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
820 uint8_t * sbb_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
821 {
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
822 return x86_rrdisp8_sizedir(out, OP_SBB, dst, src_base, disp, size, BIT_DIR);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
823 }
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 125
diff changeset
824
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
825 uint8_t * cmp_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
826 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
827 return x86_rr_sizedir(out, OP_CMP, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
828 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
829
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
830 uint8_t * cmp_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
831 {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
832 return x86_ir(out, OP_IMMED_ARITH, OP_EX_CMPI, OP_CMP, val, dst, size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
833 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
834
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
835 uint8_t * cmp_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
836 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
837 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_CMPI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
838 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
839
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
840 uint8_t * cmp_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
841 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
842 return x86_rrdisp8_sizedir(out, OP_CMP, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
843 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
844
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
845 uint8_t * cmp_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
846 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
847 return x86_rrdisp8_sizedir(out, OP_CMP, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
848 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
849
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
850 uint8_t * imul_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
851 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
852 return x86_rr_sizedir(out, OP2_IMUL | (PRE_2BYTE << 8), dst, src, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
853 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
854
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
855 uint8_t * imul_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
856 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
857 return x86_rrdisp8_sizedir(out, OP2_IMUL | (PRE_2BYTE << 8), dst, src_base, disp, size, 0);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
858 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
859
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
860 uint8_t * not_r(uint8_t * out, uint8_t dst, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
861 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
862 return x86_r_size(out, OP_NOT_NEG, OP_EX_NOT, dst, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
863 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
864
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
865 uint8_t * neg_r(uint8_t * out, uint8_t dst, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
866 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
867 return x86_r_size(out, OP_NOT_NEG, OP_EX_NEG, dst, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
868 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
869
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
870 uint8_t * not_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
871 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
872 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_NOT, dst_base, disp, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
873 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
874
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
875 uint8_t * neg_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
876 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
877 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_NEG, dst_base, disp, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
878 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
879
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
880 uint8_t * mul_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
881 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
882 return x86_r_size(out, OP_NOT_NEG, OP_EX_MUL, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
883 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
884
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
885 uint8_t * imul_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
886 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
887 return x86_r_size(out, OP_NOT_NEG, OP_EX_IMUL, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
888 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
889
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
890 uint8_t * div_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
891 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
892 return x86_r_size(out, OP_NOT_NEG, OP_EX_DIV, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
893 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
894
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
895 uint8_t * idiv_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
896 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
897 return x86_r_size(out, OP_NOT_NEG, OP_EX_IDIV, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
898 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
899
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
900 uint8_t * mul_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
901 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
902 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_MUL, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
903 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
904
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
905 uint8_t * imul_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
906 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
907 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_IMUL, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
908 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
909
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
910 uint8_t * div_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
911 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
912 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_DIV, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
913 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
914
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
915 uint8_t * idiv_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
916 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
917 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_IDIV, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
918 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
919
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
920 uint8_t * mov_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
921 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
922 return x86_rr_sizedir(out, OP_MOV, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
923 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
924
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
925 uint8_t * mov_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
926 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
927 return x86_rrdisp8_sizedir(out, OP_MOV, src, dst_base, disp, size, 0);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
928 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
929
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
930 uint8_t * mov_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
931 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
932 return x86_rrdisp8_sizedir(out, OP_MOV, dst, src_base, disp, size, BIT_DIR);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
933 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
934
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
935 uint8_t * mov_rrind(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
936 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
937 return x86_rrind_sizedir(out, OP_MOV, src, dst, size, 0);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
938 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
939
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
940 uint8_t * mov_rindr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
941 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
942 return x86_rrind_sizedir(out, OP_MOV, dst, src, size, BIT_DIR);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
943 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
944
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
945 uint8_t * mov_ir(uint8_t * out, int64_t val, uint8_t dst, uint8_t size)
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
946 {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
947 uint8_t sign_extend = 0;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
948 if (size == SZ_Q && val <= 0x7FFFFFFF && val >= -2147483648) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
949 sign_extend = 1;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
950 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
951 if (size == SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
952 *(out++) = PRE_SIZE;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
953 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
954 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
955 *out = PRE_REX;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
956 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
957 *out |= REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
958 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
959 if (dst >= R8) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
960 *out |= REX_RM_FIELD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
961 dst -= (R8 - X86_R8);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
962 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
963 out++;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
964 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
965 if (dst >= AH && dst <= BH) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
966 dst -= (AH-X86_AH);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
967 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
968 if (size == SZ_B) {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
969 *(out++) = OP_MOV_I8R | dst;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
970 } else if (size == SZ_Q && sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
971 *(out++) = OP_MOV_IEA | BIT_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
972 *(out++) = MODE_REG_DIRECT | dst;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
973 } else {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
974 *(out++) = OP_MOV_IR | dst;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
975 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
976 *(out++) = val;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
977 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
978 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
979 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
980 if (size != SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
981 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
982 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
983 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
984 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
985 if (size == SZ_Q && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
986 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
987 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
988 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
989 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
990 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
991 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
992 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
993 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
994 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
995 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
996 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
997 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
998 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
999
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1000 uint8_t * mov_irdisp8(uint8_t * out, int32_t val, uint8_t dst, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1001 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1002 if (size == SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1003 *(out++) = PRE_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1004 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1005 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1006 *out = PRE_REX;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1007 if (size == SZ_Q) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1008 *out |= REX_QUAD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1009 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1010 if (dst >= R8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1011 *out |= REX_RM_FIELD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1012 dst -= (R8 - X86_R8);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1013 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1014 out++;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1015 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1016 if (dst >= AH && dst <= BH) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1017 dst -= (AH-X86_AH);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1018 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1019 *(out++) = OP_MOV_IEA | (size == SZ_B ? 0 : BIT_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1020 *(out++) = MODE_REG_DISPLACE8 | dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1021 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1022
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1023 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1024 if (size != SZ_B) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1025 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1026 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1027 if (size != SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1028 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1029 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1030 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1031 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1032 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1033 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1034 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1035 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1036
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1037 uint8_t * mov_irind(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1038 {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1039 if (size == SZ_W) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1040 *(out++) = PRE_SIZE;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1041 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1042 if (size == SZ_Q || dst >= R8 || (size == SZ_B && dst >= RSP && dst <= RDI)) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1043 *out = PRE_REX;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1044 if (size == SZ_Q) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1045 *out |= REX_QUAD;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1046 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1047 if (dst >= R8) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1048 *out |= REX_RM_FIELD;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1049 dst -= (R8 - X86_R8);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1050 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1051 out++;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1052 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1053 if (dst >= AH && dst <= BH) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1054 dst -= (AH-X86_AH);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1055 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1056 *(out++) = OP_MOV_IEA | (size == SZ_B ? 0 : BIT_SIZE);
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1057 *(out++) = MODE_REG_INDIRECT | dst;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1058
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1059 *(out++) = val;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1060 if (size != SZ_B) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1061 val >>= 8;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1062 *(out++) = val;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1063 if (size != SZ_W) {
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1064 val >>= 8;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1065 *(out++) = val;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1066 val >>= 8;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1067 *(out++) = val;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1068 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1069 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1070 return out;
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1071 }
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
1072
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1073 uint8_t * movsx_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t src_size, uint8_t size)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1074 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1075 if (size == SZ_W) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1076 *(out++) = PRE_SIZE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1077 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1078 if (size == SZ_Q || dst >= R8 || src >= R8) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1079 *out = PRE_REX;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1080 if (size == SZ_Q) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1081 *out |= REX_QUAD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1082 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1083 if (src >= R8) {
125
dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1084 *out |= REX_RM_FIELD;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1085 src -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1086 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1087 if (dst >= R8) {
125
dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1088 *out |= REX_REG_FIELD;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1089 dst -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1090 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1091 out++;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1092 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1093 if (src_size == SZ_D) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1094 *(out++) = OP_MOVSXD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1095 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1096 *(out++) = PRE_2BYTE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1097 *(out++) = OP2_MOVSX | (src_size == SZ_B ? 0 : BIT_SIZE);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1098 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1099 *(out++) = MODE_REG_DIRECT | src | (dst << 3);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1100 return out;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1101 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1102
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1103 uint8_t * movsx_rdisp8r(uint8_t * out, uint8_t src, int8_t disp, uint8_t dst, uint8_t src_size, uint8_t size)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1104 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1105 if (size == SZ_W) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1106 *(out++) = PRE_SIZE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1107 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1108 if (size == SZ_Q || dst >= R8 || src >= R8) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1109 *out = PRE_REX;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1110 if (size == SZ_Q) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1111 *out |= REX_QUAD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1112 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1113 if (src >= R8) {
125
dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1114 *out |= REX_RM_FIELD;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1115 src -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1116 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1117 if (dst >= R8) {
125
dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
1118 *out |= REX_REG_FIELD;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1119 dst -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1120 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1121 out++;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1122 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1123 if (src_size == SZ_D) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1124 *(out++) = OP_MOVSXD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1125 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1126 *(out++) = PRE_2BYTE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1127 *(out++) = OP2_MOVSX | (src_size == SZ_B ? 0 : BIT_SIZE);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1128 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1129 *(out++) = MODE_REG_DISPLACE8 | src | (dst << 3);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1130 *(out++) = disp;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1131 return out;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1132 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1133
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1134 uint8_t * movzx_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t src_size, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1135 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1136 if (size == SZ_W) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1137 *(out++) = PRE_SIZE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1138 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1139 if (size == SZ_Q || dst >= R8 || src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1140 *out = PRE_REX;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1141 if (size == SZ_Q) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1142 *out |= REX_QUAD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1143 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1144 if (src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1145 *out |= REX_RM_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1146 src -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1147 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1148 if (dst >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1149 *out |= REX_REG_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1150 dst -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1151 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1152 out++;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1153 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1154 *(out++) = PRE_2BYTE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1155 *(out++) = OP2_MOVZX | (src_size == SZ_B ? 0 : BIT_SIZE);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1156 *(out++) = MODE_REG_DIRECT | src | (dst << 3);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1157 return out;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1158 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1159
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1160 uint8_t * movzx_rdisp8r(uint8_t * out, uint8_t src, int8_t disp, uint8_t dst, uint8_t src_size, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1161 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1162 if (size == SZ_W) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1163 *(out++) = PRE_SIZE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1164 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1165 if (size == SZ_Q || dst >= R8 || src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1166 *out = PRE_REX;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1167 if (size == SZ_Q) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1168 *out |= REX_QUAD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1169 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1170 if (src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1171 *out |= REX_RM_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1172 src -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1173 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1174 if (dst >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1175 *out |= REX_REG_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1176 dst -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1177 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1178 out++;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1179 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1180 *(out++) = PRE_2BYTE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1181 *(out++) = OP2_MOVZX | (src_size == SZ_B ? 0 : BIT_SIZE);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1182 *(out++) = MODE_REG_DISPLACE8 | src | (dst << 3);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1183 *(out++) = disp;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1184 return out;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1185 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1186
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1187 uint8_t * pushf(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1188 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1189 *(out++) = OP_PUSHF;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1190 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1191 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1192
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1193 uint8_t * popf(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1194 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1195 *(out++) = OP_POPF;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1196 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1197 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1198
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1199 uint8_t * push_r(uint8_t * out, uint8_t reg)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1200 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1201 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1202 *(out++) = PRE_REX | REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1203 reg -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1204 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1205 *(out++) = OP_PUSH | reg;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1206 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1207 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1208
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1209 uint8_t * pop_r(uint8_t * out, uint8_t reg)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1210 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1211 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1212 *(out++) = PRE_REX | REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1213 reg -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1214 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1215 *(out++) = OP_POP | reg;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1216 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1217 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1218
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1219 uint8_t * setcc_r(uint8_t * out, uint8_t cc, uint8_t dst)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1220 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1221 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1222 *(out++) = PRE_REX | REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1223 dst -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1224 } else if (dst >= RSP && dst <= RDI) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1225 *(out++) = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1226 } else if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1227 dst -= AH - X86_AH;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1228 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1229 *(out++) = PRE_2BYTE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1230 *(out++) = OP2_SETCC | cc;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1231 *(out++) = MODE_REG_DIRECT | dst;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1232 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1233 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1234
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1235 uint8_t * setcc_rind(uint8_t * out, uint8_t cc, uint8_t dst)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1236 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1237 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1238 *(out++) = PRE_REX | REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1239 dst -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1240 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1241 *(out++) = PRE_2BYTE;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1242 *(out++) = OP2_SETCC | cc;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1243 *(out++) = MODE_REG_INDIRECT | dst;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1244 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1245 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1246
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1247 uint8_t * setcc_rdisp8(uint8_t * out, uint8_t cc, uint8_t dst, int8_t disp)
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1248 {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1249 if (dst >= R8) {
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1250 *(out++) = PRE_REX | REX_RM_FIELD;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1251 dst -= R8 - X86_R8;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1252 }
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1253 *(out++) = PRE_2BYTE;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1254 *(out++) = OP2_SETCC | cc;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1255 *(out++) = MODE_REG_DISPLACE8 | dst;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1256 *(out++) = disp;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1257 return out;
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1258 }
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
1259
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1260 uint8_t * bit_rr(uint8_t * out, uint8_t op2, uint8_t src, uint8_t dst, uint8_t size)
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1261 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1262 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1263 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1264 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1265 if (size == SZ_Q || src >= R8 || dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1266 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1267 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1268 *out |= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1269 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1270 if (src >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1271 *out |= REX_REG_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1272 src -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1273 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1274 if (dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1275 *out |= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1276 dst -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1277 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1278 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1279 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1280 *(out++) = PRE_2BYTE;
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1281 *(out++) = op2;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1282 *(out++) = MODE_REG_DIRECT | dst | (src << 3);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1283 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1284 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1285
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1286 uint8_t * bit_rrdisp8(uint8_t * out, uint8_t op2, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1287 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1288 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1289 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1290 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1291 if (size == SZ_Q || src >= R8 || dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1292 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1293 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1294 *out |= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1295 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1296 if (src >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1297 *out |= REX_REG_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1298 src -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1299 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1300 if (dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1301 *out |= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1302 dst_base -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1303 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1304 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1305 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1306 *(out++) = PRE_2BYTE;
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1307 *(out++) = op2;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1308 *(out++) = MODE_REG_DISPLACE8 | dst_base | (src << 3);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1309 *(out++) = dst_disp;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1310 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1311 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1312
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1313 uint8_t * bit_ir(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size)
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1314 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1315 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1316 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1317 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1318 if (size == SZ_Q || dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1319 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1320 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1321 *out |= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1322 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1323 if (dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1324 *out |= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1325 dst -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1326 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1327 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1328 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1329 *(out++) = PRE_2BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1330 *(out++) = OP2_BTX_I;
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1331 *(out++) = MODE_REG_DIRECT | dst | (op_ex << 3);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1332 *(out++) = val;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1333 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1334 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1335
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1336 uint8_t * bit_irdisp8(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1337 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1338 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1339 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1340 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1341 if (size == SZ_Q || dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1342 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1343 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1344 *out |= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1345 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1346 if (dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1347 *out |= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1348 dst_base -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1349 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1350 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1351 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1352 *(out++) = PRE_2BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1353 *(out++) = OP2_BTX_I;
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1354 *(out++) = MODE_REG_DISPLACE8 | dst_base | (op_ex << 3);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1355 *(out++) = dst_disp;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1356 *(out++) = val;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1357 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1358 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
1359
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1360 uint8_t * bt_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1361 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1362 return bit_rr(out, OP2_BT, src, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1363 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1364
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1365 uint8_t * bt_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1366 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1367 return bit_rrdisp8(out, OP2_BT, src, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1368 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1369
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1370 uint8_t * bt_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1371 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1372 return bit_ir(out, OP_EX_BT, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1373 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1374
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1375 uint8_t * bt_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1376 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1377 return bit_irdisp8(out, OP_EX_BT, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1378 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1379
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1380 uint8_t * bts_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1381 {
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
1382 return bit_rr(out, OP2_BTS, src, dst, size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1383 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1384
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1385 uint8_t * bts_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1386 {
194
811163790e6c Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
1387 return bit_rrdisp8(out, OP2_BTS, src, dst_base, dst_disp, size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1388 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1389
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1390 uint8_t * bts_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1391 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1392 return bit_ir(out, OP_EX_BTS, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1393 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1394
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1395 uint8_t * bts_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1396 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1397 return bit_irdisp8(out, OP_EX_BTS, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1398 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1399
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1400 uint8_t * btr_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1401 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1402 return bit_rr(out, OP2_BTR, src, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1403 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1404
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1405 uint8_t * btr_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1406 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1407 return bit_rrdisp8(out, OP2_BTR, src, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1408 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1409
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1410 uint8_t * btr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1411 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1412 return bit_ir(out, OP_EX_BTR, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1413 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1414
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1415 uint8_t * btr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1416 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1417 return bit_irdisp8(out, OP_EX_BTR, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1418 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1419
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1420 uint8_t * btc_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1421 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1422 return bit_rr(out, OP2_BTC, src, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1423 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1424
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1425 uint8_t * btc_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1426 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1427 return bit_rrdisp8(out, OP2_BTC, src, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1428 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1429
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1430 uint8_t * btc_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1431 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1432 return bit_ir(out, OP_EX_BTC, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1433 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1434
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1435 uint8_t * btc_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1436 {
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1437 return bit_irdisp8(out, OP_EX_BTC, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1438 }
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 117
diff changeset
1439
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1440 uint8_t * jcc(uint8_t * out, uint8_t cc, uint8_t * dest)
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1441 {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1442 ptrdiff_t disp = dest-(out+2);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1443 if (disp <= 0x7F && disp >= -0x80) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1444 *(out++) = OP_JCC | cc;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1445 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1446 } else {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1447 disp = dest-(out+6);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1448 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1449 *(out++) = PRE_2BYTE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1450 *(out++) = OP2_JCC | cc;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1451 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1452 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1453 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1454 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1455 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1456 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1457 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1458 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1459 printf("%p - %p = %lX\n", dest, out + 6, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1460 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1461 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1462 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1463 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1464 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1465
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1466 uint8_t * jmp(uint8_t * out, uint8_t * dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1467 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1468 ptrdiff_t disp = dest-(out+2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1469 if (disp <= 0x7F && disp >= -0x80) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1470 *(out++) = OP_JMP_BYTE;
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1471 *(out++) = disp;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1472 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1473 disp = dest-(out+5);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1474 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1475 *(out++) = OP_JMP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1476 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1477 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1478 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1479 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1480 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1481 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1482 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1483 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1484 printf("%p - %p = %lX\n", dest, out + 6, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1485 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1486 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1487 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1488 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1489 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1490
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1491 uint8_t * jmp_r(uint8_t * out, uint8_t dst)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1492 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1493 *(out++) = OP_SINGLE_EA;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1494 *(out++) = MODE_REG_DIRECT | dst | (OP_EX_JMP_EA << 3);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
1495 return out;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1496 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1497
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1498 uint8_t * call(uint8_t * out, uint8_t * fun)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1499 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1500 ptrdiff_t disp = fun-(out+5);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1501 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1502 *(out++) = OP_CALL;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1503 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1504 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1505 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1506 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1507 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1508 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1509 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1510 } else {
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1511 //TODO: Implement far call???
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1512 printf("%p - %p = %lX\n", fun, out + 5, disp);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1513 return NULL;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1514 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1515 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1516 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1517
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1518 uint8_t * call_r(uint8_t * out, uint8_t dst)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1519 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1520 *(out++) = OP_SINGLE_EA;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1521 *(out++) = MODE_REG_DIRECT | dst | (OP_EX_CALL_EA << 3);
117
fb7944d3ed5c Fix call_r in gen_x86 so that it properly returns a pointer to the location after the generated instruction
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
1522 return out;
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1523 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
1524
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1525 uint8_t * retn(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1526 {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1527 *(out++) = OP_RETN;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1528 return out;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1529 }
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1530
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1531 uint8_t * cdq(uint8_t * out)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1532 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1533 *(out++) = OP_CDQ;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1534 return out;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
1535 }
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1536
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1537 uint8_t * loop(uint8_t * out, uint8_t * dst)
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1538 {
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1539 ptrdiff_t disp = dst-(out+2);
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1540 *(out++) = OP_LOOP;
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1541 *(out++) = disp;
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1542 return out;
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
1543 }