repos/blastem: gen_x86.c annotate

annotate gen_x86.c @ 478:2e4a4188cfb0

Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.

author	Mike Pavone <pavone@retrodev.com>
date	Tue, 17 Sep 2013 00:11:45 -0700
parents	140af5509ce7
children	0bf5e6b672fe

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	2 Copyright 2013 Michael Pavone
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	3 This file is part of BlastEm.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	5 */
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "68kinst.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include <stddef.h>
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <stdio.h>
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	10 #include <stdlib.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define REX_RM_FIELD 0x1
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 #define REX_SIB_FIELD 0x2
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define REX_REG_FIELD 0x4
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define REX_QUAD 0x8
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define OP_ADD 0x00
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define OP_OR 0x08
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define PRE_2BYTE 0x0F
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define OP_ADC 0x10
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 #define OP_SBB 0x18
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 #define OP_AND 0x20
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 #define OP_SUB 0x28
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 #define OP_XOR 0x30
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 #define OP_CMP 0x38
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 #define PRE_REX 0x40
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 #define OP_PUSH 0x50
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 #define OP_POP 0x58
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	29 #define OP_MOVSXD 0x63
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 #define PRE_SIZE 0x66
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 #define OP_JCC 0x70
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 #define OP_IMMED_ARITH 0x80
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	33 #define OP_XCHG 0x86
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 #define OP_MOV 0x88
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	35 #define OP_XCHG_AX 0x90
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	36 #define OP_CDQ 0x99
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 #define OP_PUSHF 0x9C
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 #define OP_POPF 0x9D
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 #define OP_MOV_I8R 0xB0
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 #define OP_MOV_IR 0xB8
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	41 #define OP_SHIFTROT_IR 0xC0
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 #define OP_RETN 0xC3
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	43 #define OP_MOV_IEA 0xC6
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	44 #define OP_SHIFTROT_1 0xD0
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	45 #define OP_SHIFTROT_CL 0xD2
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	46 #define OP_LOOP 0xE2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 #define OP_CALL 0xE8
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	48 #define OP_JMP 0xE9
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	49 #define OP_JMP_BYTE 0xEB
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	50 #define OP_NOT_NEG 0xF6
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	51 #define OP_SINGLE_EA 0xFF
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	52
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 #define OP2_JCC 0x80
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 #define OP2_SETCC 0x90
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	55 #define OP2_BT 0xA3
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	56 #define OP2_BTS 0xAB
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	57 #define OP2_IMUL 0xAF
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	58 #define OP2_BTR 0xB3
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	59 #define OP2_BTX_I 0xBA
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	60 #define OP2_BTC 0xBB
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	61 #define OP2_MOVSX 0xBE
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	62 #define OP2_MOVZX 0xB6
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	63
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 #define OP_EX_ADDI 0x0
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 #define OP_EX_ORI 0x1
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 #define OP_EX_ADCI 0x2
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 #define OP_EX_SBBI 0x3
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 #define OP_EX_ANDI 0x4
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 #define OP_EX_SUBI 0x5
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 #define OP_EX_XORI 0x6
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 #define OP_EX_CMPI 0x7
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	72
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	73 #define OP_EX_ROL 0x0
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	74 #define OP_EX_ROR 0x1
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	75 #define OP_EX_RCL 0x2
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	76 #define OP_EX_RCR 0x3
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	77 #define OP_EX_SHL 0x4
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	78 #define OP_EX_SHR 0x5
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	79 #define OP_EX_SAL 0x6 //identical to SHL
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	80 #define OP_EX_SAR 0x7
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	81
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	82 #define OP_EX_BT 0x4
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	83 #define OP_EX_BTS 0x5
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	84 #define OP_EX_BTR 0x6
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	85 #define OP_EX_BTC 0x7
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	86
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	87 #define OP_EX_TEST_I 0x0
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	88 #define OP_EX_NOT 0x2
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	89 #define OP_EX_NEG 0x3
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	90 #define OP_EX_MUL 0x4
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	91 #define OP_EX_IMUL 0x5
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	92 #define OP_EX_DIV 0x6
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	93 #define OP_EX_IDIV 0x7
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	94
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	95 #define OP_EX_INC 0x0
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	96 #define OP_EX_DEC 0x1
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	97 #define OP_EX_CALL_EA 0x2
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	98 #define OP_EX_JMP_EA 0x4
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	99 #define OP_EX_PUSH_EA 0x6
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	100
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 #define BIT_IMMED_RAX 0x4
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 #define BIT_DIR 0x2
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 #define BIT_SIZE 0x1
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	104
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	105
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 enum {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 X86_RAX = 0,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 X86_RCX,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 X86_RDX,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 X86_RBX,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 X86_RSP,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 X86_RBP,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 X86_RSI,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 X86_RDI,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 X86_AH=4,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 X86_CH,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 X86_DH,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 X86_BH,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 X86_R8=0,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	120 X86_R9,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 X86_R10,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 X86_R11,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 X86_R12,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 X86_R13,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 X86_R14,
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 X86_R15
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 } x86_regs_enc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	128
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	129 uint8_t * x86_rr_sizedir(uint8_t * out, uint16_t opcode, uint8_t src, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	134 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	135 if (size == SZ_B && dst >= RSP && dst <= RDI) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 opcode \|= BIT_DIR;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 tmp = dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 dst = src;
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	139 src = tmp;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	140 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 if (size == SZ_Q \|\| src >= R8 \|\| dst >= R8 \|\| (size == SZ_B && src >= RSP && src <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 *out = PRE_REX;
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	143 if (src >= AH && src <= BH \|\| dst >= AH && dst <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	144 fprintf(stderr, "attempt to use *H reg in an instruction requiring REX prefix. opcode = %X\n", opcode);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	145 exit(1);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	146 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 *out \|= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 if (src >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 *out \|= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 src -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 *out \|= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 dst -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 out++;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	160 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 if (src >= AH && src <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 src -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 dst -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 } else {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 opcode \|= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 }
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	170 if (opcode >= 0x100) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	171 *(out++) = opcode >> 8;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	172 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	173 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	174 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	175 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 *(out++) = MODE_REG_DIRECT \| dst \| (src << 3);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	179
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	180 uint8_t * x86_rrdisp8_sizedir(uint8_t * out, uint16_t opcode, uint8_t reg, uint8_t base, int8_t disp, uint8_t size, uint8_t dir)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 if (size == SZ_Q \|\| reg >= R8 \|\| base >= R8 \|\| (size == SZ_B && reg >= RSP && reg <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 *out = PRE_REX;
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	189 if (reg >= AH && reg <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	190 fprintf(stderr, "attempt to use *H reg in an instruction requiring REX prefix. opcode = %X\n", opcode);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	191 exit(1);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	192 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 *out \|= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 *out \|= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 reg -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 if (base >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 *out \|= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 base -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 out++;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 if (reg >= AH && reg <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 reg -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 } else {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 opcode \|= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 }
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	213 opcode \|= dir;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	214 if (opcode >= 0x100) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	215 *(out++) = opcode >> 8;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	216 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	217 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	218 *(out++) = opcode;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	219 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 *(out++) = MODE_REG_DISPLACE8 \| base \| (reg << 3);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	221 if (base == RSP) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	222 //add SIB byte, with no index and RSP as base
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	223 *(out++) = (RSP << 3) \| RSP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	224 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	228
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	229 uint8_t * x86_rrdisp32_sizedir(uint8_t * out, uint16_t opcode, uint8_t reg, uint8_t base, int32_t disp, uint8_t size, uint8_t dir)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	230 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	231 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	232 uint8_t tmp;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	233 if (size == SZ_W) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	234 *(out++) = PRE_SIZE;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	235 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	236 if (size == SZ_Q \|\| reg >= R8 \|\| base >= R8 \|\| (size == SZ_B && reg >= RSP && reg <= RDI)) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	237 *out = PRE_REX;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	238 if (reg >= AH && reg <= BH) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	239 fprintf(stderr, "attempt to use *H reg in an instruction requiring REX prefix. opcode = %X\n", opcode);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	240 exit(1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	241 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	242 if (size == SZ_Q) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	243 *out \|= REX_QUAD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	244 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	245 if (reg >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	246 *out \|= REX_REG_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	247 reg -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	248 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	249 if (base >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	250 *out \|= REX_RM_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	251 base -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	252 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	253 out++;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	254 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	255 if (size == SZ_B) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	256 if (reg >= AH && reg <= BH) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	257 reg -= (AH-X86_AH);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	258 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	259 } else {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	260 opcode \|= BIT_SIZE;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	261 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	262 opcode \|= dir;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	263 if (opcode >= 0x100) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	264 *(out++) = opcode >> 8;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	265 *(out++) = opcode;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	266 } else {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	267 *(out++) = opcode;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	268 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	269 *(out++) = MODE_REG_DISPLACE32 \| base \| (reg << 3);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	270 if (base == RSP) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	271 //add SIB byte, with no index and RSP as base
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	272 *(out++) = (RSP << 3) \| RSP;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	273 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	274 *(out++) = disp;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	275 *(out++) = disp >> 8;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	276 *(out++) = disp >> 16;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	277 *(out++) = disp >> 24;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	278 return out;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	279 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	280
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 uint8_t * x86_rrind_sizedir(uint8_t * out, uint8_t opcode, uint8_t reg, uint8_t base, uint8_t size, uint8_t dir)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 uint8_t tmp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 if (size == SZ_W) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 *(out++) = PRE_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 if (size == SZ_Q \|\| reg >= R8 \|\| base >= R8 \|\| (size == SZ_B && reg >= RSP && reg <= RDI)) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 *out = PRE_REX;
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	290 if (reg >= AH && reg <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	291 fprintf(stderr, "attempt to use *H reg in an instruction requiring REX prefix. opcode = %X\n", opcode);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	292 exit(1);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	293 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	294 if (size == SZ_Q) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 *out \|= REX_QUAD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 *out \|= REX_REG_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 reg -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 if (base >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 *out \|= REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 base -= (R8 - X86_R8);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 out++;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 if (size == SZ_B) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 if (reg >= AH && reg <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	309 reg -= (AH-X86_AH);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	310 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 } else {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 opcode \|= BIT_SIZE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	313 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	314 *(out++) = opcode \| dir;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 *(out++) = MODE_REG_INDIRECT \| base \| (reg << 3);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	316 if (base == RSP) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	317 //add SIB byte, with no index and RSP as base
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	318 *(out++) = (RSP << 3) \| RSP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	319 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	321 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	322
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	323 uint8_t * x86_rrindex_sizedir(uint8_t * out, uint8_t opcode, uint8_t reg, uint8_t base, uint8_t index, uint8_t scale, uint8_t size, uint8_t dir)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	324 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	325 //TODO: Deal with the fact that AH, BH, CH and DH can only be in the R/M param when there's a REX prefix
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	326 uint8_t tmp;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	327 if (size == SZ_W) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	328 *(out++) = PRE_SIZE;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	329 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	330 if (size == SZ_Q \|\| reg >= R8 \|\| base >= R8 \|\| (size == SZ_B && reg >= RSP && reg <= RDI)) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	331 *out = PRE_REX;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	332 if (reg >= AH && reg <= BH) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	333 fprintf(stderr, "attempt to use *H reg in an instruction requiring REX prefix. opcode = %X\n", opcode);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	334 exit(1);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	335 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	336 if (size == SZ_Q) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	337 *out \|= REX_QUAD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	338 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	339 if (reg >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	340 *out \|= REX_REG_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	341 reg -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	342 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	343 if (base >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	344 *out \|= REX_RM_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	345 base -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	346 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	347 if (index >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	348 *out \|= REX_SIB_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	349 index -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	350 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	351 out++;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	352 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	353 if (size == SZ_B) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	354 if (reg >= AH && reg <= BH) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	355 reg -= (AH-X86_AH);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	356 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	357 } else {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	358 opcode \|= BIT_SIZE;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	359 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	360 *(out++) = opcode \| dir;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	361 *(out++) = MODE_REG_INDIRECT \| base \| (RSP << 3);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	362 if (base == RSP) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	363 if (scale == 4) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	364 scale = 3;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	365 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	366 *(out++) = scale << 6 \| (index << 3) \| base;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	367 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	368 return out;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	369 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	370
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	371 uint8_t * x86_r_size(uint8_t * out, uint8_t opcode, uint8_t opex, uint8_t dst, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	372 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	373 uint8_t tmp;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	374 if (size == SZ_W) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	375 *(out++) = PRE_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	376 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	377 if (size == SZ_Q \|\| dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	378 *out = PRE_REX;
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	379 if (dst >= AH && dst <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	380 fprintf(stderr, "attempt to use *H reg in an instruction requiring REX prefix. opcode = %X\n", opcode);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	381 exit(1);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 241 diff changeset	382 }
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	383 if (size == SZ_Q) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	384 *out \|= REX_QUAD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	385 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	386 if (dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	387 *out \|= REX_RM_FIELD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	388 dst -= (R8 - X86_R8);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	389 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	390 out++;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	391 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	392 if (size == SZ_B) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	393 if (dst >= AH && dst <= BH) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	394 dst -= (AH-X86_AH);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	395 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	396 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	397 opcode \|= BIT_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	398 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	399 *(out++) = opcode;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	400 *(out++) = MODE_REG_DIRECT \| dst \| (opex << 3);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	401 return out;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	402 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	403
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	404 uint8_t * x86_rdisp8_size(uint8_t * out, uint8_t opcode, uint8_t opex, uint8_t dst, int8_t disp, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	405 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	406 uint8_t tmp;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	407 if (size == SZ_W) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	408 *(out++) = PRE_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	409 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	410 if (size == SZ_Q \|\| dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	411 *out = PRE_REX;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	412 if (size == SZ_Q) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	413 *out \|= REX_QUAD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	414 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	415 if (dst >= R8) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	416 *out \|= REX_RM_FIELD;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	417 dst -= (R8 - X86_R8);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	418 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	419 out++;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	420 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	421 if (size != SZ_B) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	422 opcode \|= BIT_SIZE;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	423 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	424 *(out++) = opcode;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	425 *(out++) = MODE_REG_DISPLACE8 \| dst \| (opex << 3);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	426 *(out++) = disp;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	427 return out;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	428 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	429
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	430 uint8_t * x86_ir(uint8_t * out, uint8_t opcode, uint8_t op_ex, uint8_t al_opcode, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	431 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	432 uint8_t sign_extend = 0;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	433 if ((size == SZ_D \|\| size == SZ_Q) && val <= 0x7F && val >= -0x80) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	434 sign_extend = 1;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	435 opcode \|= BIT_DIR;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	436 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	437 if (size == SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	438 *(out++) = PRE_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	439 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	440 if (dst == RAX && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	441 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	442 al_opcode \|= BIT_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	443 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	444 *out = PRE_REX \| REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	445 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	446 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 *(out++) = al_opcode \| BIT_IMMED_RAX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 } else {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	449 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	450 *out = PRE_REX;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	451 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	452 *out \|= REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	453 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	454 if (dst >= R8) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	455 *out \|= REX_RM_FIELD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	456 dst -= (R8 - X86_R8);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	457 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	458 out++;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	459 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	460 if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	461 dst -= (AH-X86_AH);
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	462 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	463 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	464 opcode \|= BIT_SIZE;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	465 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	466 *(out++) = opcode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	467 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	468 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	469 *(out++) = val;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	470 if (size != SZ_B && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	471 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	472 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	473 if (size != SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	474 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	475 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	476 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	477 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	478 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	479 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	480 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	481 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	482
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	483 uint8_t * x86_irdisp8(uint8_t * out, uint8_t opcode, uint8_t op_ex, int32_t val, uint8_t dst, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	484 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	485 uint8_t sign_extend = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	486 if ((size == SZ_D \|\| size == SZ_Q) && val <= 0x7F && val >= -0x80) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	487 sign_extend = 1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	488 opcode \|= BIT_DIR;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	489 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	490 if (size == SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	491 *(out++) = PRE_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	492 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	493
349 ad493d38964e Fix some minor copy pasta bugs that resulted in an unnecessary REX prefix being generated for some instructions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	494 if (size == SZ_Q \|\| dst >= R8) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	495 *out = PRE_REX;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	496 if (size == SZ_Q) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	497 *out \|= REX_QUAD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	498 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	499 if (dst >= R8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	500 *out \|= REX_RM_FIELD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	501 dst -= (R8 - X86_R8);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	502 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	503 out++;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	504 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	505 if (size != SZ_B) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	506 opcode \|= BIT_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	507 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	508 *(out++) = opcode;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	509 *(out++) = MODE_REG_DISPLACE8 \| dst \| (op_ex << 3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	510 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	511 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	512 if (size != SZ_B && !sign_extend) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	513 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	514 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	515 if (size != SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	516 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	517 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	518 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	519 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	520 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	521 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	522 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	523 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	524
420 9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	525 uint8_t * x86_irdisp32(uint8_t * out, uint8_t opcode, uint8_t op_ex, int32_t val, uint8_t dst, int32_t disp, uint8_t size)
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	526 {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	527 uint8_t sign_extend = 0;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	528 if ((size == SZ_D \|\| size == SZ_Q) && val <= 0x7F && val >= -0x80) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	529 sign_extend = 1;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	530 opcode \|= BIT_DIR;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	531 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	532 if (size == SZ_W) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	533 *(out++) = PRE_SIZE;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	534 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	535
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	536 if (size == SZ_Q \|\| dst >= R8) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	537 *out = PRE_REX;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	538 if (size == SZ_Q) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	539 *out \|= REX_QUAD;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	540 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	541 if (dst >= R8) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	542 *out \|= REX_RM_FIELD;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	543 dst -= (R8 - X86_R8);
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	544 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	545 out++;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	546 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	547 if (size != SZ_B) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	548 opcode \|= BIT_SIZE;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	549 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	550 *(out++) = opcode;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	551 *(out++) = MODE_REG_DISPLACE32 \| dst \| (op_ex << 3);
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	552 *(out++) = disp;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	553 disp >>= 8;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	554 *(out++) = disp;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	555 disp >>= 8;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	556 *(out++) = disp;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	557 disp >>= 8;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	558 *(out++) = disp;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	559 *(out++) = val;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	560 if (size != SZ_B && !sign_extend) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	561 val >>= 8;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	562 *(out++) = val;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	563 if (size != SZ_W) {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	564 val >>= 8;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	565 *(out++) = val;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	566 val >>= 8;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	567 *(out++) = val;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	568 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	569 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	570 return out;
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	571 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	572
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	573
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	574 uint8_t * x86_shiftrot_ir(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	575 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	576 if (size == SZ_W) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	577 *(out++) = PRE_SIZE;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	578 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	579 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	580 *out = PRE_REX;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	581 if (size == SZ_Q) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	582 *out \|= REX_QUAD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	583 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	584 if (dst >= R8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	585 *out \|= REX_RM_FIELD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	586 dst -= (R8 - X86_R8);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	587 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	588 out++;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	589 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	590 if (dst >= AH && dst <= BH) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	591 dst -= (AH-X86_AH);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	592 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	593
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	594 *(out++) = (val == 1 ? OP_SHIFTROT_1: OP_SHIFTROT_IR) \| (size == SZ_B ? 0 : BIT_SIZE);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	595 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	596 if (val != 1) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	597 *(out++) = val;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	598 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	599 return out;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	600 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	601
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	602 uint8_t * x86_shiftrot_irdisp8(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	603 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	604 if (size == SZ_W) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	605 *(out++) = PRE_SIZE;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	606 }
349 ad493d38964e Fix some minor copy pasta bugs that resulted in an unnecessary REX prefix being generated for some instructions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	607 if (size == SZ_Q \|\| dst >= R8) {
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	608 *out = PRE_REX;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	609 if (size == SZ_Q) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	610 *out \|= REX_QUAD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	611 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	612 if (dst >= R8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	613 *out \|= REX_RM_FIELD;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	614 dst -= (R8 - X86_R8);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	615 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	616 out++;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	617 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	618 if (dst >= AH && dst <= BH) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	619 dst -= (AH-X86_AH);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	620 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	621
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	622 *(out++) = (val == 1 ? OP_SHIFTROT_1: OP_SHIFTROT_IR) \| (size == SZ_B ? 0 : BIT_SIZE);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	623 *(out++) = MODE_REG_DISPLACE8 \| dst \| (op_ex << 3);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	624 *(out++) = disp;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	625 if (val != 1) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	626 *(out++) = val;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	627 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	628 return out;
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	629 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	630
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	631 uint8_t * x86_shiftrot_clr(uint8_t * out, uint8_t op_ex, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	632 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	633 if (size == SZ_W) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	634 *(out++) = PRE_SIZE;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	635 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	636 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	637 *out = PRE_REX;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	638 if (size == SZ_Q) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	639 *out \|= REX_QUAD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	640 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	641 if (dst >= R8) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	642 *out \|= REX_RM_FIELD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	643 dst -= (R8 - X86_R8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	644 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	645 out++;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	646 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	647 if (dst >= AH && dst <= BH) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	648 dst -= (AH-X86_AH);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	649 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	650
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	651 *(out++) = OP_SHIFTROT_CL \| (size == SZ_B ? 0 : BIT_SIZE);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	652 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	653 return out;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	654 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	655
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	656 uint8_t * x86_shiftrot_clrdisp8(uint8_t * out, uint8_t op_ex, uint8_t dst, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	657 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	658 if (size == SZ_W) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	659 *(out++) = PRE_SIZE;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	660 }
349 ad493d38964e Fix some minor copy pasta bugs that resulted in an unnecessary REX prefix being generated for some instructions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	661 if (size == SZ_Q \|\| dst >= R8) {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	662 *out = PRE_REX;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	663 if (size == SZ_Q) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	664 *out \|= REX_QUAD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	665 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	666 if (dst >= R8) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	667 *out \|= REX_RM_FIELD;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	668 dst -= (R8 - X86_R8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	669 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	670 out++;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	671 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	672 if (dst >= AH && dst <= BH) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	673 dst -= (AH-X86_AH);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	674 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	675
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	676 *(out++) = OP_SHIFTROT_CL \| (size == SZ_B ? 0 : BIT_SIZE);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	677 *(out++) = MODE_REG_DISPLACE8 \| dst \| (op_ex << 3);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	678 *(out++) = disp;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	679 return out;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	680 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	681
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	682 uint8_t * rol_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	683 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	684 return x86_shiftrot_ir(out, OP_EX_ROL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	685 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	686
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	687 uint8_t * ror_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	688 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	689 return x86_shiftrot_ir(out, OP_EX_ROR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	690 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	691
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	692 uint8_t * rcl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	693 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	694 return x86_shiftrot_ir(out, OP_EX_RCL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	695 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	696
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	697 uint8_t * rcr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	698 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	699 return x86_shiftrot_ir(out, OP_EX_RCR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	700 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	701
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	702 uint8_t * shl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	703 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	704 return x86_shiftrot_ir(out, OP_EX_SHL, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	705 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	706
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	707 uint8_t * shr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	708 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	709 return x86_shiftrot_ir(out, OP_EX_SHR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	710 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	711
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	712 uint8_t * sar_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	713 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	714 return x86_shiftrot_ir(out, OP_EX_SAR, val, dst, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	715 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	716
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	717 uint8_t * rol_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	718 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	719 return x86_shiftrot_irdisp8(out, OP_EX_ROL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	720 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	721
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	722 uint8_t * ror_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	723 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	724 return x86_shiftrot_irdisp8(out, OP_EX_ROR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	725 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	726
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	727 uint8_t * rcl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	728 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	729 return x86_shiftrot_irdisp8(out, OP_EX_RCL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	730 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	731
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	732 uint8_t * rcr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	733 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	734 return x86_shiftrot_irdisp8(out, OP_EX_RCR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	735 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	736
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	737 uint8_t * shl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	738 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	739 return x86_shiftrot_irdisp8(out, OP_EX_SHL, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	740 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	741
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	742 uint8_t * shr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	743 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	744 return x86_shiftrot_irdisp8(out, OP_EX_SHR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	745 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	746
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	747 uint8_t * sar_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size)
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	748 {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	749 return x86_shiftrot_irdisp8(out, OP_EX_SAR, val, dst_base, disp, size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	750 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	751
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	752 uint8_t * rol_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	753 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	754 return x86_shiftrot_clr(out, OP_EX_ROL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	755 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	756
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	757 uint8_t * ror_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	758 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	759 return x86_shiftrot_clr(out, OP_EX_ROR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	760 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	761
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	762 uint8_t * rcl_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	763 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	764 return x86_shiftrot_clr(out, OP_EX_RCL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	765 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	766
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	767 uint8_t * rcr_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	768 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	769 return x86_shiftrot_clr(out, OP_EX_RCR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	770 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	771
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	772 uint8_t * shl_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	773 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	774 return x86_shiftrot_clr(out, OP_EX_SHL, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	775 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	776
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	777 uint8_t * shr_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	778 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	779 return x86_shiftrot_clr(out, OP_EX_SHR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	780 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	781
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	782 uint8_t * sar_clr(uint8_t * out, uint8_t dst, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	783 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	784 return x86_shiftrot_clr(out, OP_EX_SAR, dst, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	785 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	786
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	787 uint8_t * rol_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	788 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	789 return x86_shiftrot_clrdisp8(out, OP_EX_ROL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	790 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	791
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	792 uint8_t * ror_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	793 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	794 return x86_shiftrot_clrdisp8(out, OP_EX_ROR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	795 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	796
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	797 uint8_t * rcl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	798 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	799 return x86_shiftrot_clrdisp8(out, OP_EX_RCL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	800 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	801
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	802 uint8_t * rcr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	803 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	804 return x86_shiftrot_clrdisp8(out, OP_EX_RCR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	805 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	806
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	807 uint8_t * shl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	808 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	809 return x86_shiftrot_clrdisp8(out, OP_EX_SHL, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	810 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	811
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	812 uint8_t * shr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	813 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	814 return x86_shiftrot_clrdisp8(out, OP_EX_SHR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	815 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	816
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	817 uint8_t * sar_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	818 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	819 return x86_shiftrot_clrdisp8(out, OP_EX_SAR, dst_base, disp, size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	820 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	821
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	822 uint8_t * add_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	823 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	824 return x86_rr_sizedir(out, OP_ADD, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	825 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	826
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	827 uint8_t * add_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	828 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	829 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ADDI, OP_ADD, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	830 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	831
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	832 uint8_t * add_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	833 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	834 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ADDI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	835 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	836
420 9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	837 uint8_t * add_irdisp32(uint8_t * out, int32_t val, uint8_t dst_base, int32_t disp, uint8_t size)
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	838 {
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	839 return x86_irdisp32(out, OP_IMMED_ARITH, OP_EX_ADDI, val, dst_base, disp, size);
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	840 }
9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 349 diff changeset	841
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	842 uint8_t * add_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	843 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	844 return x86_rrdisp8_sizedir(out, OP_ADD, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	845 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	846
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	847 uint8_t * add_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	848 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	849 return x86_rrdisp8_sizedir(out, OP_ADD, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	850 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	851
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	852 uint8_t * adc_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	853 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	854 return x86_rr_sizedir(out, OP_ADC, src, dst, size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	855 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	856
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	857 uint8_t * adc_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	858 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	859 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ADCI, OP_ADC, val, dst, size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	860 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	861
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	862 uint8_t * adc_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	863 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	864 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ADCI, val, dst_base, disp, size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	865 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	866
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	867 uint8_t * adc_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	868 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	869 return x86_rrdisp8_sizedir(out, OP_ADC, src, dst_base, disp, size, 0);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	870 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	871
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	872 uint8_t * adc_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	873 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	874 return x86_rrdisp8_sizedir(out, OP_ADC, dst, src_base, disp, size, BIT_DIR);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	875 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	876
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	877 uint8_t * or_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	878 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	879 return x86_rr_sizedir(out, OP_OR, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	880 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	881 uint8_t * or_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	882 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	883 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ORI, OP_OR, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	884 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	885
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	886 uint8_t * or_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	887 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	888 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ORI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	889 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	890
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	891 uint8_t * or_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	892 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	893 return x86_rrdisp8_sizedir(out, OP_OR, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	894 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	895
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	896 uint8_t * or_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	897 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	898 return x86_rrdisp8_sizedir(out, OP_OR, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	899 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	900
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	901 uint8_t * and_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	902 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	903 return x86_rr_sizedir(out, OP_AND, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	904 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	905
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	906 uint8_t * and_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	907 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	908 return x86_ir(out, OP_IMMED_ARITH, OP_EX_ANDI, OP_AND, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	909 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	910
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	911 uint8_t * and_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	912 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	913 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_ANDI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	914 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	915
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	916 uint8_t * and_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	917 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	918 return x86_rrdisp8_sizedir(out, OP_AND, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	919 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	920
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	921 uint8_t * and_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	922 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	923 return x86_rrdisp8_sizedir(out, OP_AND, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	924 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	925
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	926 uint8_t * xor_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	927 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	928 return x86_rr_sizedir(out, OP_XOR, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	929 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	930
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	931 uint8_t * xor_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	932 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	933 return x86_ir(out, OP_IMMED_ARITH, OP_EX_XORI, OP_XOR, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	934 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	935
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	936 uint8_t * xor_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	937 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	938 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_XORI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	939 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	940
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	941 uint8_t * xor_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	942 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	943 return x86_rrdisp8_sizedir(out, OP_XOR, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	944 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	945
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	946 uint8_t * xor_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	947 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	948 return x86_rrdisp8_sizedir(out, OP_XOR, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	949 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	950
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	951 uint8_t * sub_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	952 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	953 return x86_rr_sizedir(out, OP_SUB, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	954 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	955
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	956 uint8_t * sub_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	957 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	958 return x86_ir(out, OP_IMMED_ARITH, OP_EX_SUBI, OP_SUB, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	959 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	960
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	961 uint8_t * sub_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	962 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	963 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_SUBI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	964 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	965
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	966 uint8_t * sub_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	967 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	968 return x86_rrdisp8_sizedir(out, OP_SUB, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	969 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	970
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	971 uint8_t * sub_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	972 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	973 return x86_rrdisp8_sizedir(out, OP_SUB, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	974 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	975
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	976 uint8_t * sbb_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	977 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	978 return x86_rr_sizedir(out, OP_SBB, src, dst, size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	979 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	980
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	981 uint8_t * sbb_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	982 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	983 return x86_ir(out, OP_IMMED_ARITH, OP_EX_SBBI, OP_SBB, val, dst, size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	984 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	985
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	986 uint8_t * sbb_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	987 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	988 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_SBBI, val, dst_base, disp, size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	989 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	990
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	991 uint8_t * sbb_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	992 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	993 return x86_rrdisp8_sizedir(out, OP_SBB, src, dst_base, disp, size, 0);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	994 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	995
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	996 uint8_t * sbb_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	997 {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	998 return x86_rrdisp8_sizedir(out, OP_SBB, dst, src_base, disp, size, BIT_DIR);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	999 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 125 diff changeset	1000
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1001 uint8_t * cmp_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1002 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1003 return x86_rr_sizedir(out, OP_CMP, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1004 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1005
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1006 uint8_t * cmp_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1007 {
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1008 return x86_ir(out, OP_IMMED_ARITH, OP_EX_CMPI, OP_CMP, val, dst, size);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1009 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1010
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1011 uint8_t * cmp_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1012 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1013 return x86_irdisp8(out, OP_IMMED_ARITH, OP_EX_CMPI, val, dst_base, disp, size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1014 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1015
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1016 uint8_t * cmp_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1017 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1018 return x86_rrdisp8_sizedir(out, OP_CMP, src, dst_base, disp, size, 0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1019 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1020
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1021 uint8_t * cmp_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1022 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1023 return x86_rrdisp8_sizedir(out, OP_CMP, dst, src_base, disp, size, BIT_DIR);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1024 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1025
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1026 uint8_t * imul_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1027 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1028 return x86_rr_sizedir(out, OP2_IMUL \| (PRE_2BYTE << 8), dst, src, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1029 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1030
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1031 uint8_t * imul_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1032 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1033 return x86_rrdisp8_sizedir(out, OP2_IMUL \| (PRE_2BYTE << 8), dst, src_base, disp, size, 0);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1034 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1035
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1036 uint8_t * not_r(uint8_t * out, uint8_t dst, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1037 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1038 return x86_r_size(out, OP_NOT_NEG, OP_EX_NOT, dst, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1039 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1040
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1041 uint8_t * neg_r(uint8_t * out, uint8_t dst, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1042 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1043 return x86_r_size(out, OP_NOT_NEG, OP_EX_NEG, dst, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1044 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1045
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1046 uint8_t * not_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1047 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1048 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_NOT, dst_base, disp, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1049 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1050
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1051 uint8_t * neg_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1052 {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1053 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_NEG, dst_base, disp, size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1054 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1055
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1056 uint8_t * mul_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1057 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1058 return x86_r_size(out, OP_NOT_NEG, OP_EX_MUL, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1059 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1060
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1061 uint8_t * imul_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1062 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1063 return x86_r_size(out, OP_NOT_NEG, OP_EX_IMUL, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1064 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1065
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1066 uint8_t * div_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1067 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1068 return x86_r_size(out, OP_NOT_NEG, OP_EX_DIV, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1069 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1070
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1071 uint8_t * idiv_r(uint8_t * out, uint8_t dst, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1072 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1073 return x86_r_size(out, OP_NOT_NEG, OP_EX_IDIV, dst, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1074 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1075
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1076 uint8_t * mul_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1077 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1078 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_MUL, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1079 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1080
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1081 uint8_t * imul_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1082 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1083 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_IMUL, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1084 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1085
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1086 uint8_t * div_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1087 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1088 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_DIV, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1089 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1090
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1091 uint8_t * idiv_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1092 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1093 return x86_rdisp8_size(out, OP_NOT_NEG, OP_EX_IDIV, dst_base, disp, size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1094 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1095
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1096 uint8_t * mov_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1097 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1098 return x86_rr_sizedir(out, OP_MOV, src, dst, size);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1099 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1100
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1101 uint8_t * mov_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1102 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1103 return x86_rrdisp8_sizedir(out, OP_MOV, src, dst_base, disp, size, 0);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1104 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1105
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1106 uint8_t * mov_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1107 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1108 return x86_rrdisp8_sizedir(out, OP_MOV, dst, src_base, disp, size, BIT_DIR);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1109 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1110
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1111 uint8_t * mov_rrdisp32(uint8_t * out, uint8_t src, uint8_t dst_base, int32_t disp, uint8_t size)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1112 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1113 return x86_rrdisp32_sizedir(out, OP_MOV, src, dst_base, disp, size, 0);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1114 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1115
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1116 uint8_t * mov_rdisp32r(uint8_t * out, uint8_t src_base, int32_t disp, uint8_t dst, uint8_t size)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1117 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1118 return x86_rrdisp32_sizedir(out, OP_MOV, dst, src_base, disp, size, BIT_DIR);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1119 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1120
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1121 uint8_t * mov_rrind(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1122 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1123 return x86_rrind_sizedir(out, OP_MOV, src, dst, size, 0);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1124 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1125
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1126 uint8_t * mov_rindr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1127 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1128 return x86_rrind_sizedir(out, OP_MOV, dst, src, size, BIT_DIR);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1129 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1130
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1131 uint8_t * mov_rrindex(uint8_t * out, uint8_t src, uint8_t dst_base, uint8_t dst_index, uint8_t scale, uint8_t size)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1132 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1133 return x86_rrindex_sizedir(out, OP_MOV, src, dst_base, dst_index, scale, size, 0);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1134 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1135
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1136 uint8_t * mov_rindexr(uint8_t * out, uint8_t src_base, uint8_t src_index, uint8_t scale, uint8_t dst, uint8_t size)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1137 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1138 return x86_rrindex_sizedir(out, OP_MOV, dst, src_base, src_index, scale, size, BIT_DIR);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1139 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1140
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1141 uint8_t * mov_ir(uint8_t * out, int64_t val, uint8_t dst, uint8_t size)
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1142 {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1143 uint8_t sign_extend = 0;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1144 if (size == SZ_Q && val <= 0x7FFFFFFF && val >= -2147483648) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1145 sign_extend = 1;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1146 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1147 if (size == SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1148 *(out++) = PRE_SIZE;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1149 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1150 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1151 *out = PRE_REX;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1152 if (size == SZ_Q) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1153 *out \|= REX_QUAD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1154 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1155 if (dst >= R8) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1156 *out \|= REX_RM_FIELD;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1157 dst -= (R8 - X86_R8);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1158 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1159 out++;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1160 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1161 if (dst >= AH && dst <= BH) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1162 dst -= (AH-X86_AH);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1163 }
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1164 if (size == SZ_B) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1165 *(out++) = OP_MOV_I8R \| dst;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1166 } else if (size == SZ_Q && sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1167 *(out++) = OP_MOV_IEA \| BIT_SIZE;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1168 *(out++) = MODE_REG_DIRECT \| dst;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1169 } else {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1170 *(out++) = OP_MOV_IR \| dst;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1171 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1172 *(out++) = val;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1173 if (size != SZ_B) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1174 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1175 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1176 if (size != SZ_W) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1177 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1178 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1179 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1180 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1181 if (size == SZ_Q && !sign_extend) {
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1182 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1183 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1184 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1185 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1186 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1187 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1188 val >>= 8;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1189 *(out++) = val;
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1190 }
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1191 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1192 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1193 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1194 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1195
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1196 uint8_t * mov_irdisp8(uint8_t * out, int32_t val, uint8_t dst, int8_t disp, uint8_t size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1197 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1198 if (size == SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1199 *(out++) = PRE_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1200 }
349 ad493d38964e Fix some minor copy pasta bugs that resulted in an unnecessary REX prefix being generated for some instructions Mike Pavone <pavone@retrodev.com> parents: 343 diff changeset	1201 if (size == SZ_Q \|\| dst >= R8) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1202 *out = PRE_REX;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1203 if (size == SZ_Q) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1204 *out \|= REX_QUAD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1205 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1206 if (dst >= R8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1207 *out \|= REX_RM_FIELD;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1208 dst -= (R8 - X86_R8);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1209 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1210 out++;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1211 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1212 if (dst >= AH && dst <= BH) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1213 dst -= (AH-X86_AH);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1214 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1215 *(out++) = OP_MOV_IEA \| (size == SZ_B ? 0 : BIT_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1216 *(out++) = MODE_REG_DISPLACE8 \| dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1217 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1218
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1219 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1220 if (size != SZ_B) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1221 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1222 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1223 if (size != SZ_W) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1224 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1225 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1226 val >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1227 *(out++) = val;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1228 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1229 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1230 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1231 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1232
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1233 uint8_t * mov_irind(uint8_t * out, int32_t val, uint8_t dst, uint8_t size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1234 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1235 if (size == SZ_W) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1236 *(out++) = PRE_SIZE;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1237 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1238 if (size == SZ_Q \|\| dst >= R8 \|\| (size == SZ_B && dst >= RSP && dst <= RDI)) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1239 *out = PRE_REX;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1240 if (size == SZ_Q) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1241 *out \|= REX_QUAD;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1242 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1243 if (dst >= R8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1244 *out \|= REX_RM_FIELD;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1245 dst -= (R8 - X86_R8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1246 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1247 out++;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1248 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1249 if (dst >= AH && dst <= BH) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1250 dst -= (AH-X86_AH);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1251 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1252 *(out++) = OP_MOV_IEA \| (size == SZ_B ? 0 : BIT_SIZE);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1253 *(out++) = MODE_REG_INDIRECT \| dst;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1254
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1255 *(out++) = val;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1256 if (size != SZ_B) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1257 val >>= 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1258 *(out++) = val;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1259 if (size != SZ_W) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1260 val >>= 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1261 *(out++) = val;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1262 val >>= 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1263 *(out++) = val;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1264 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1265 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1266 return out;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1267 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1268
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1269 uint8_t * movsx_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t src_size, uint8_t size)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1270 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1271 if (size == SZ_W) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1272 *(out++) = PRE_SIZE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1273 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1274 if (size == SZ_Q \|\| dst >= R8 \|\| src >= R8) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1275 *out = PRE_REX;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1276 if (size == SZ_Q) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1277 *out \|= REX_QUAD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1278 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1279 if (src >= R8) {
125 dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1280 *out \|= REX_RM_FIELD;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1281 src -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1282 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1283 if (dst >= R8) {
125 dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1284 *out \|= REX_REG_FIELD;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1285 dst -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1286 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1287 out++;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1288 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1289 if (src_size == SZ_D) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1290 *(out++) = OP_MOVSXD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1291 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1292 *(out++) = PRE_2BYTE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1293 *(out++) = OP2_MOVSX \| (src_size == SZ_B ? 0 : BIT_SIZE);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1294 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1295 *(out++) = MODE_REG_DIRECT \| src \| (dst << 3);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1296 return out;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1297 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1298
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1299 uint8_t * movsx_rdisp8r(uint8_t * out, uint8_t src, int8_t disp, uint8_t dst, uint8_t src_size, uint8_t size)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1300 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1301 if (size == SZ_W) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1302 *(out++) = PRE_SIZE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1303 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1304 if (size == SZ_Q \|\| dst >= R8 \|\| src >= R8) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1305 *out = PRE_REX;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1306 if (size == SZ_Q) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1307 *out \|= REX_QUAD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1308 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1309 if (src >= R8) {
125 dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1310 *out \|= REX_RM_FIELD;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1311 src -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1312 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1313 if (dst >= R8) {
125 dc5fc3adf705 Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1314 *out \|= REX_REG_FIELD;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1315 dst -= (R8 - X86_R8);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1316 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1317 out++;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1318 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1319 if (src_size == SZ_D) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1320 *(out++) = OP_MOVSXD;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1321 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1322 *(out++) = PRE_2BYTE;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1323 *(out++) = OP2_MOVSX \| (src_size == SZ_B ? 0 : BIT_SIZE);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1324 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1325 *(out++) = MODE_REG_DISPLACE8 \| src \| (dst << 3);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1326 *(out++) = disp;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1327 return out;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1328 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1329
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1330 uint8_t * movzx_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t src_size, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1331 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1332 if (size == SZ_W) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1333 *(out++) = PRE_SIZE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1334 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1335 if (size == SZ_Q \|\| dst >= R8 \|\| src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1336 *out = PRE_REX;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1337 if (size == SZ_Q) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1338 *out \|= REX_QUAD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1339 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1340 if (src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1341 *out \|= REX_RM_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1342 src -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1343 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1344 if (dst >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1345 *out \|= REX_REG_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1346 dst -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1347 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1348 out++;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1349 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1350 *(out++) = PRE_2BYTE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1351 *(out++) = OP2_MOVZX \| (src_size == SZ_B ? 0 : BIT_SIZE);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1352 *(out++) = MODE_REG_DIRECT \| src \| (dst << 3);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1353 return out;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1354 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1355
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1356 uint8_t * movzx_rdisp8r(uint8_t * out, uint8_t src, int8_t disp, uint8_t dst, uint8_t src_size, uint8_t size)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1357 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1358 if (size == SZ_W) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1359 *(out++) = PRE_SIZE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1360 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1361 if (size == SZ_Q \|\| dst >= R8 \|\| src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1362 *out = PRE_REX;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1363 if (size == SZ_Q) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1364 *out \|= REX_QUAD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1365 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1366 if (src >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1367 *out \|= REX_RM_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1368 src -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1369 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1370 if (dst >= R8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1371 *out \|= REX_REG_FIELD;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1372 dst -= (R8 - X86_R8);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1373 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1374 out++;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1375 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1376 *(out++) = PRE_2BYTE;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1377 *(out++) = OP2_MOVZX \| (src_size == SZ_B ? 0 : BIT_SIZE);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1378 *(out++) = MODE_REG_DISPLACE8 \| src \| (dst << 3);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1379 *(out++) = disp;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1380 return out;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1381 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1382
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1383 uint8_t * xchg_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1384 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1385 //TODO: Use OP_XCHG_AX when one of the registers is AX, EAX or RAX
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1386 uint8_t tmp;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1387 if (size == SZ_W) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1388 *(out++) = PRE_SIZE;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1389 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1390 if (size == SZ_B && dst >= RSP && dst <= RDI) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1391 tmp = dst;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1392 dst = src;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1393 src = tmp;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1394 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1395 if (size == SZ_Q \|\| src >= R8 \|\| dst >= R8 \|\| (size == SZ_B && src >= RSP && src <= RDI)) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1396 *out = PRE_REX;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1397 if (size == SZ_Q) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1398 *out \|= REX_QUAD;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1399 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1400 if (src >= R8) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1401 *out \|= REX_REG_FIELD;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1402 src -= (R8 - X86_R8);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1403 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1404 if (dst >= R8) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1405 *out \|= REX_RM_FIELD;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1406 dst -= (R8 - X86_R8);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1407 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1408 out++;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1409 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1410 uint8_t opcode = OP_XCHG;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1411 if (size == SZ_B) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1412 if (src >= AH && src <= BH) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1413 src -= (AH-X86_AH);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1414 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1415 if (dst >= AH && dst <= BH) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1416 dst -= (AH-X86_AH);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1417 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1418 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1419 opcode \|= BIT_SIZE;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1420 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1421 *(out++) = opcode;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1422 *(out++) = MODE_REG_DIRECT \| dst \| (src << 3);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1423 return out;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1424 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1425
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1426 uint8_t * pushf(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1427 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1428 *(out++) = OP_PUSHF;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1429 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1430 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1431
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1432 uint8_t * popf(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1433 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1434 *(out++) = OP_POPF;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1435 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1436 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1437
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1438 uint8_t * push_r(uint8_t * out, uint8_t reg)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1439 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1440 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1441 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1442 reg -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1443 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1444 *(out++) = OP_PUSH \| reg;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1445 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1446 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1447
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1448 uint8_t * pop_r(uint8_t * out, uint8_t reg)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1449 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1450 if (reg >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1451 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1452 reg -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1453 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1454 *(out++) = OP_POP \| reg;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1455 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1456 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1457
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1458 uint8_t * setcc_r(uint8_t * out, uint8_t cc, uint8_t dst)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1459 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1460 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1461 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1462 dst -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1463 } else if (dst >= RSP && dst <= RDI) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1464 *(out++) = PRE_REX;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1465 } else if (dst >= AH && dst <= BH) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1466 dst -= AH - X86_AH;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1467 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1468 *(out++) = PRE_2BYTE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1469 *(out++) = OP2_SETCC \| cc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1470 *(out++) = MODE_REG_DIRECT \| dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1471 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1472 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1473
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1474 uint8_t * setcc_rind(uint8_t * out, uint8_t cc, uint8_t dst)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1475 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1476 if (dst >= R8) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1477 *(out++) = PRE_REX \| REX_RM_FIELD;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1478 dst -= R8 - X86_R8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1479 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1480 *(out++) = PRE_2BYTE;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1481 *(out++) = OP2_SETCC \| cc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1482 *(out++) = MODE_REG_INDIRECT \| dst;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1483 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1484 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1485
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1486 uint8_t * setcc_rdisp8(uint8_t * out, uint8_t cc, uint8_t dst, int8_t disp)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1487 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1488 if (dst >= R8) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1489 *(out++) = PRE_REX \| REX_RM_FIELD;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1490 dst -= R8 - X86_R8;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1491 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1492 *(out++) = PRE_2BYTE;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1493 *(out++) = OP2_SETCC \| cc;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1494 *(out++) = MODE_REG_DISPLACE8 \| dst;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1495 *(out++) = disp;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1496 return out;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1497 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	1498
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1499 uint8_t * bit_rr(uint8_t * out, uint8_t op2, uint8_t src, uint8_t dst, uint8_t size)
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1500 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1501 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1502 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1503 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1504 if (size == SZ_Q \|\| src >= R8 \|\| dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1505 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1506 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1507 *out \|= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1508 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1509 if (src >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1510 *out \|= REX_REG_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1511 src -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1512 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1513 if (dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1514 *out \|= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1515 dst -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1516 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1517 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1518 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1519 *(out++) = PRE_2BYTE;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1520 *(out++) = op2;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1521 *(out++) = MODE_REG_DIRECT \| dst \| (src << 3);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1522 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1523 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1524
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1525 uint8_t * bit_rrdisp8(uint8_t * out, uint8_t op2, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1526 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1527 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1528 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1529 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1530 if (size == SZ_Q \|\| src >= R8 \|\| dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1531 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1532 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1533 *out \|= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1534 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1535 if (src >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1536 *out \|= REX_REG_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1537 src -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1538 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1539 if (dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1540 *out \|= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1541 dst_base -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1542 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1543 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1544 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1545 *(out++) = PRE_2BYTE;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1546 *(out++) = op2;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1547 *(out++) = MODE_REG_DISPLACE8 \| dst_base \| (src << 3);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1548 *(out++) = dst_disp;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1549 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1550 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1551
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1552 uint8_t * bit_rrdisp32(uint8_t * out, uint8_t op2, uint8_t src, uint8_t dst_base, int32_t dst_disp, uint8_t size)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1553 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1554 if (size == SZ_W) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1555 *(out++) = PRE_SIZE;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1556 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1557 if (size == SZ_Q \|\| src >= R8 \|\| dst_base >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1558 *out = PRE_REX;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1559 if (size == SZ_Q) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1560 *out \|= REX_QUAD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1561 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1562 if (src >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1563 *out \|= REX_REG_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1564 src -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1565 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1566 if (dst_base >= R8) {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1567 *out \|= REX_RM_FIELD;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1568 dst_base -= (R8 - X86_R8);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1569 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1570 out++;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1571 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1572 *(out++) = PRE_2BYTE;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1573 *(out++) = op2;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1574 *(out++) = MODE_REG_DISPLACE32 \| dst_base \| (src << 3);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1575 *(out++) = dst_disp;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1576 *(out++) = dst_disp >> 8;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1577 *(out++) = dst_disp >> 16;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1578 *(out++) = dst_disp >> 24;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1579 return out;
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1580 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1581
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1582 uint8_t * bit_ir(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size)
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1583 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1584 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1585 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1586 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1587 if (size == SZ_Q \|\| dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1588 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1589 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1590 *out \|= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1591 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1592 if (dst >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1593 *out \|= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1594 dst -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1595 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1596 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1597 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1598 *(out++) = PRE_2BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1599 *(out++) = OP2_BTX_I;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1600 *(out++) = MODE_REG_DIRECT \| dst \| (op_ex << 3);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1601 *(out++) = val;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1602 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1603 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1604
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1605 uint8_t * bit_irdisp8(uint8_t * out, uint8_t op_ex, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1606 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1607 if (size == SZ_W) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1608 *(out++) = PRE_SIZE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1609 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1610 if (size == SZ_Q \|\| dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1611 *out = PRE_REX;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1612 if (size == SZ_Q) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1613 *out \|= REX_QUAD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1614 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1615 if (dst_base >= R8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1616 *out \|= REX_RM_FIELD;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1617 dst_base -= (R8 - X86_R8);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1618 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1619 out++;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1620 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1621 *(out++) = PRE_2BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1622 *(out++) = OP2_BTX_I;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1623 *(out++) = MODE_REG_DISPLACE8 \| dst_base \| (op_ex << 3);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1624 *(out++) = dst_disp;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1625 *(out++) = val;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1626 return out;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1627 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1628
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1629 uint8_t * bt_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1630 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1631 return bit_rr(out, OP2_BT, src, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1632 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1633
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1634 uint8_t * bt_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1635 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1636 return bit_rrdisp8(out, OP2_BT, src, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1637 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1638
343 467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1639 uint8_t * bt_rrdisp32(uint8_t * out, uint8_t src, uint8_t dst_base, int32_t dst_disp, uint8_t size)
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1640 {
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1641 return bit_rrdisp32(out, OP2_BT, src, dst_base, dst_disp, size);
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1642 }
467bfa17004a Mostly working runtime generation of memory map read/write functions Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1643
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1644 uint8_t * bt_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1645 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1646 return bit_ir(out, OP_EX_BT, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1647 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1648
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1649 uint8_t * bt_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1650 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1651 return bit_irdisp8(out, OP_EX_BT, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1652 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1653
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1654 uint8_t * bts_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1655 {
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	1656 return bit_rr(out, OP2_BTS, src, dst, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1657 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1658
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1659 uint8_t * bts_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1660 {
194 811163790e6c Implement ABCD an SBCD. Fix BTEST with register source. Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	1661 return bit_rrdisp8(out, OP2_BTS, src, dst_base, dst_disp, size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1662 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1663
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1664 uint8_t * bts_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1665 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1666 return bit_ir(out, OP_EX_BTS, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1667 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1668
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1669 uint8_t * bts_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1670 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1671 return bit_irdisp8(out, OP_EX_BTS, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1672 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1673
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1674 uint8_t * btr_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1675 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1676 return bit_rr(out, OP2_BTR, src, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1677 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1678
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1679 uint8_t * btr_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1680 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1681 return bit_rrdisp8(out, OP2_BTR, src, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1682 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1683
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1684 uint8_t * btr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1685 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1686 return bit_ir(out, OP_EX_BTR, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1687 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1688
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1689 uint8_t * btr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1690 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1691 return bit_irdisp8(out, OP_EX_BTR, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1692 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1693
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1694 uint8_t * btc_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1695 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1696 return bit_rr(out, OP2_BTC, src, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1697 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1698
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1699 uint8_t * btc_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1700 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1701 return bit_rrdisp8(out, OP2_BTC, src, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1702 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1703
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1704 uint8_t * btc_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1705 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1706 return bit_ir(out, OP_EX_BTC, val, dst, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1707 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1708
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1709 uint8_t * btc_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size)
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1710 {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1711 return bit_irdisp8(out, OP_EX_BTC, val, dst_base, dst_disp, size);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1712 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 117 diff changeset	1713
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1714 uint8_t * jcc(uint8_t * out, uint8_t cc, uint8_t * dest)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1715 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1716 ptrdiff_t disp = dest-(out+2);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1717 if (disp <= 0x7F && disp >= -0x80) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1718 *(out++) = OP_JCC \| cc;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1719 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1720 } else {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1721 disp = dest-(out+6);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1722 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1723 *(out++) = PRE_2BYTE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1724 *(out++) = OP2_JCC \| cc;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1725 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1726 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1727 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1728 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1729 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1730 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1731 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1732 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1733 printf("%p - %p = %lX\n", dest, out + 6, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1734 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1735 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1736 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1737 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1738 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1739
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1740 uint8_t * jmp(uint8_t * out, uint8_t * dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1741 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1742 ptrdiff_t disp = dest-(out+2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1743 if (disp <= 0x7F && disp >= -0x80) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1744 *(out++) = OP_JMP_BYTE;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1745 *(out++) = disp;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1746 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1747 disp = dest-(out+5);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1748 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1749 *(out++) = OP_JMP;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1750 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1751 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1752 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1753 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1754 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1755 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1756 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1757 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1758 printf("%p - %p = %lX\n", dest, out + 6, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1759 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1760 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1761 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1762 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1763 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1764
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1765 uint8_t * jmp_r(uint8_t * out, uint8_t dst)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1766 {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	1767 if (dst >= R8) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	1768 dst -= R8 - X86_R8;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	1769 *(out++) = PRE_REX \| REX_RM_FIELD;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 207 diff changeset	1770 }
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1771 *(out++) = OP_SINGLE_EA;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1772 *(out++) = MODE_REG_DIRECT \| dst \| (OP_EX_JMP_EA << 3);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1773 return out;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1774 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1775
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1776 uint8_t * call(uint8_t * out, uint8_t * fun)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1777 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1778 ptrdiff_t disp = fun-(out+5);
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1779 if (disp <= 0x7FFFFFFF && disp >= -2147483648) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1780 *(out++) = OP_CALL;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1781 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1782 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1783 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1784 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1785 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1786 disp >>= 8;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1787 *(out++) = disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1788 } else {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1789 //TODO: Implement far call???
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	1790 printf("%p - %p = %lX\n", fun, out + 5, disp);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1791 return NULL;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1792 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1793 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1794 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1795
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1796 uint8_t * call_r(uint8_t * out, uint8_t dst)
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1797 {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1798 *(out++) = OP_SINGLE_EA;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1799 *(out++) = MODE_REG_DIRECT \| dst \| (OP_EX_CALL_EA << 3);
117 fb7944d3ed5c Fix call_r in gen_x86 so that it properly returns a pointer to the location after the generated instruction Mike Pavone <pavone@retrodev.com> parents: 112 diff changeset	1800 return out;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1801 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1802
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1803 uint8_t * retn(uint8_t * out)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1804 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1805 *(out++) = OP_RETN;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1806 return out;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1807 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1808
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1809 uint8_t * cdq(uint8_t * out)
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1810 {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1811 *(out++) = OP_CDQ;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1812 return out;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	1813 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1814
207 c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1815 uint8_t * loop(uint8_t * out, uint8_t * dst)
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1816 {
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1817 ptrdiff_t disp = dst-(out+2);
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1818 *(out++) = OP_LOOP;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1819 *(out++) = disp;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1820 return out;
c82f65a87a53 Fix overflow flag on ASL Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	1821 }

Mercurial > repos > blastem

annotate gen_x86.c @ 478:2e4a4188cfb0