Mercurial > repos > blastem
annotate jagcpu.c @ 1944:357878be8be6
Fix vgmplay target
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 26 Apr 2020 14:56:44 -0700 |
parents | c1e78a101912 |
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rev | line source |
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1093
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1 #include <stdint.h> |
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2 #include <stdio.h> |
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3 #include "jagcpu.h" |
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4 |
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5 char *gpu_mnemonics[] = { |
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6 "add", |
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7 "addc", |
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8 "addq", |
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9 "addqt", |
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10 "sub", |
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11 "subc", |
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12 "subq", |
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13 "subqt", |
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14 "neg", |
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15 "and", |
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16 "or", |
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17 "xor", |
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18 "not", |
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19 "btst", |
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20 "bset", |
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21 "bclr", |
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22 "mult", |
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23 "imult", |
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24 "imultn", |
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25 "resmac", |
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26 "imacn", |
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27 "div", |
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28 "abs", |
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29 "sh", |
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30 "shlq", |
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31 "shrq", |
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32 "sha", |
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33 "sharq", |
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34 "ror", |
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35 "rorq", |
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36 "cmp", |
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37 "cmpq", |
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38 "sat8", |
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39 "sat16", |
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40 "move", |
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41 "moveq", |
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42 "moveta", |
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43 "movefa", |
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44 "movei", |
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45 "loadb", |
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46 "loadw", |
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47 "load", |
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48 "loadp", |
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49 "load", //r14 relative |
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50 "load", //r15 relative |
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51 "storeb", |
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52 "storew", |
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53 "store", |
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54 "storep", |
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55 "store", //r14 relative |
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56 "store", //r15 relative |
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57 "move", //PC |
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58 "jump", |
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59 "jr", |
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60 "mmult", |
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61 "mtoi", |
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62 "normi", |
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63 "nop", |
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64 "load", //r14 indexed |
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65 "load", //r15 indexed |
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66 "store", //r14 indexed |
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67 "store", //r15 indexed |
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68 "sat24", |
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69 "pack", |
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70 "unpack" |
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71 }; |
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72 |
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73 char *dsp_mnemonics[DSP_ADDQMOD+1] = { |
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74 [DSP_SUBQMOD] = "subqmod", |
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75 [DSP_SAT16S] = "sat16s", |
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76 [DSP_SAT32S] = "sat32s", |
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77 [DSP_MIRROR] = "mirror", |
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78 [DSP_ADDQMOD] = "addqmod" |
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79 }; |
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80 |
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81 void init_dsp_mnemonic_table() |
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82 { |
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83 static uint8_t init_done; |
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84 if (init_done) { |
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85 return; |
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86 } |
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87 for (int i = 0; i < DSP_ADDQMOD; i++) |
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88 { |
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89 if (!dsp_mnemonics[i]) { |
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90 dsp_mnemonics[i] = gpu_mnemonics[i]; |
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91 } |
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92 } |
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93 init_done = 1; |
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94 } |
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95 |
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96 uint16_t jag_opcode(uint16_t inst, uint8_t is_gpu) |
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97 { |
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98 uint16_t opcode = inst >> 10; |
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99 if (is_gpu && opcode == GPU_PACK && (inst & 0x20)) { |
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100 return GPU_UNPACK; |
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101 } |
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102 return opcode; |
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103 } |
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104 |
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105 uint16_t jag_reg2(uint16_t inst) |
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106 { |
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107 return inst & 0x1F; |
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108 } |
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109 |
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110 uint16_t jag_reg1(uint16_t inst) |
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111 { |
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112 return inst >> 5 & 0x1F; |
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113 } |
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114 |
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115 //moveq and bit instructions should just use jag_reg1 instead |
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116 uint32_t jag_quick(uint16_t inst) |
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117 { |
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118 uint32_t val = inst >> 5 & 0x1F; |
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119 return val ? val : 32; |
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120 } |
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121 |
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122 uint8_t is_quick_1_32_opcode(uint16_t opcode, uint8_t is_gpu) |
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123 { |
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124 return opcode == JAG_ADDQ |
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125 || opcode == JAG_ADDQT |
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126 || opcode == JAG_SUBQ |
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127 || opcode == JAG_SUBQT |
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128 || opcode == JAG_SHLQ |
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129 || opcode == JAG_SHRQ |
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130 || opcode == JAG_SHARQ |
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131 || opcode == JAG_RORQ |
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132 || (!is_gpu && ( |
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133 opcode == DSP_SUBQMOD |
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134 || opcode == DSP_ADDQMOD |
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135 )); |
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136 } |
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137 |
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138 uint8_t is_quick_0_31_opcode(uint16_t opcode) |
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139 { |
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140 return opcode == JAG_MOVEQ |
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141 || opcode == JAG_BTST |
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142 || opcode == JAG_BSET |
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143 || opcode == JAG_BCLR; |
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144 } |
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145 |
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146 uint8_t is_load(uint16_t opcode, uint8_t is_gpu) |
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147 { |
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148 return opcode == JAG_LOAD |
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149 || opcode == JAG_LOADB |
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150 || opcode == JAG_LOADW |
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151 || (is_gpu && opcode == GPU_LOADP); |
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152 } |
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153 |
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154 uint8_t is_store(uint16_t opcode, uint8_t is_gpu) |
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155 { |
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156 return opcode == JAG_STORE |
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157 || opcode == JAG_STOREB |
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158 || opcode == JAG_STOREW |
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159 || (is_gpu && opcode == GPU_STOREP); |
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160 } |
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161 |
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162 uint8_t is_single_source(uint16_t opcode, uint8_t is_gpu) |
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163 { |
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164 return opcode == JAG_NEG |
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165 || opcode == JAG_NOT |
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166 || opcode == JAG_ABS |
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167 || opcode == GPU_SAT16 //no is_gpu check needed as DSP_SAT16S is also single source |
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168 || (is_gpu && ( |
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169 opcode == GPU_SAT8 |
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170 || opcode == GPU_SAT24 |
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171 || opcode == GPU_PACK |
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172 || opcode == GPU_UNPACK |
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173 )) |
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174 || (!is_gpu && ( |
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175 opcode == DSP_SAT32S |
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176 || opcode == DSP_MIRROR |
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177 )); |
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178 } |
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179 |
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180 char * jag_cc_names[] = { |
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181 "t", |
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182 "ne", |
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183 "eq", |
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184 "f", |
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185 "cc", |
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186 "hi", |
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187 "eq_cc", |
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188 "f", |
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189 "cs", |
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190 "ne_cs", |
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191 "eq_cs", |
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192 "f", |
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193 "f", |
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194 "f", |
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195 "f", |
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196 "f" |
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197 "t_alt", |
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198 "ne_alt", |
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199 "eq_alt", |
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200 "f", |
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201 "pl", |
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202 "ne_pl", |
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203 "eq_pl", |
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204 "f", |
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205 "mi", |
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206 "ne_mi", |
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207 "eq_mi" |
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208 }; |
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209 |
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210 char * jag_cc(uint16_t inst) |
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211 { |
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212 uint16_t ccnum = jag_reg2(inst); |
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213 if (ccnum >= sizeof(jag_cc_names)/sizeof(*jag_cc_names)) { |
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214 return jag_cc_names[3]; |
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215 } |
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216 return jag_cc_names[ccnum]; |
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217 } |
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218 |
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219 uint8_t jag_is_alwyas_falsse(uint16_t cond) |
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220 { |
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221 return (cond & 3) == 3 || (cond && 0xC) == 0xC; |
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222 } |
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223 |
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224 uint32_t jag_jr_dest(uint16_t inst, uint32_t address) |
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225 { |
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226 uint32_t rel = jag_reg1(inst); |
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227 if (rel & 0x10) { |
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228 rel |= 0xFFFFFFE0; |
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229 } |
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230 return address + 2 + rel*2; |
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231 } |
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232 |
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233 int jag_cpu_disasm(uint16_t **stream, uint32_t address, char *dst, uint8_t is_gpu, uint8_t labels) |
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234 { |
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235 uint16_t inst = **stream; |
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236 (*stream)++; |
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237 uint16_t opcode = jag_opcode(inst, is_gpu); |
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238 char **mnemonics; |
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239 if (is_gpu) { |
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240 mnemonics = gpu_mnemonics; |
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241 } else { |
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242 init_dsp_mnemonic_table(); |
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243 mnemonics = dsp_mnemonics; |
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244 } |
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245 switch (opcode) |
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246 { |
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247 case JAG_MOVEI: { |
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248 uint32_t immed = **stream; |
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249 (*stream)++; |
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250 immed |= **stream << 16; |
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251 (*stream)++; |
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252 return sprintf(dst, "%s $%X, r%d", mnemonics[opcode], immed, jag_reg2(inst)); |
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253 } |
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254 case JAG_JR: |
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255 return sprintf(dst, |
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256 labels ? "%s %s, ADR_%X" : "%s %s, $W%X", |
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257 mnemonics[opcode], jag_cc(inst), jag_jr_dest(inst, address) |
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258 ); |
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Initial stab at jaguar disassemler
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259 case JAG_JUMP: |
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260 return sprintf(dst, "%s %s, (r%d)", mnemonics[opcode], jag_cc(inst), jag_reg1(inst)); |
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261 case JAG_LOAD_R14_REL: |
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262 case JAG_LOAD_R15_REL: |
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263 return sprintf(dst, "%s (r%d+%d), r%d", |
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264 mnemonics[opcode], |
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265 opcode == JAG_LOAD_R14_REL ? 14 : 15, |
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266 jag_quick(inst), |
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267 jag_reg2(inst) |
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268 ); |
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269 break; |
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270 case JAG_STORE_R14_REL: |
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271 case JAG_STORE_R15_REL: |
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272 return sprintf(dst, "%s r%d, (r%d+%d)", |
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273 mnemonics[opcode], |
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274 jag_reg2(inst), |
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275 opcode == JAG_STORE_R14_REL ? 14 : 15, |
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276 jag_quick(inst) |
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277 ); |
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parents:
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278 break; |
920d796ea6a2
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279 case JAG_LOAD_R14_INDEXED: |
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280 case JAG_LOAD_R15_INDEXED: |
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281 return sprintf(dst, "%s (r%d+r%d), r%d", |
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282 mnemonics[opcode], |
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283 opcode == JAG_LOAD_R14_INDEXED ? 14 : 15, |
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284 jag_reg1(inst), |
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285 jag_reg2(inst) |
920d796ea6a2
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286 ); |
920d796ea6a2
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parents:
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287 break; |
920d796ea6a2
Correct disassembly of r14/r15 relative loads and stores
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parents:
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288 case JAG_STORE_R14_INDEXED: |
920d796ea6a2
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289 case JAG_STORE_R15_INDEXED: |
920d796ea6a2
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290 return sprintf(dst, "%s r%d, (r%d+r%d)", |
920d796ea6a2
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291 mnemonics[opcode], |
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parents:
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292 jag_reg2(inst), |
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Correct disassembly of r14/r15 relative loads and stores
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293 opcode == JAG_STORE_R14_INDEXED ? 14 : 15, |
920d796ea6a2
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294 jag_reg1(inst) |
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295 ); |
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parents:
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296 break; |
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4987fddd42a0
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297 default: |
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298 if (is_quick_1_32_opcode(opcode, is_gpu)) { |
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299 return sprintf(dst, "%s %d, r%d", mnemonics[opcode], jag_quick(inst), jag_reg2(inst)); |
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300 } else if (is_quick_0_31_opcode(opcode)) { |
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parents:
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301 return sprintf(dst, "%s %d, r%d", mnemonics[opcode], jag_reg1(inst), jag_reg2(inst)); |
1096
1ab30d427db8
Better disassembly of GPU/DSP load store instructions
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302 } else if (is_load(opcode, is_gpu)) { |
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303 return sprintf(dst, "%s (r%d), r%d", mnemonics[opcode], jag_reg1(inst), jag_reg2(inst)); |
1ab30d427db8
Better disassembly of GPU/DSP load store instructions
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304 } else if (is_store(opcode, is_gpu)) { |
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305 return sprintf(dst, "%s r%d, (r%d)", mnemonics[opcode], jag_reg2(inst), jag_reg1(inst)); |
1093
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parents:
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306 } else { |
1094
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Michael Pavone <pavone@retrodev.com>
parents:
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307 return sprintf(dst, "%s r%d, r%d", mnemonics[opcode], jag_reg1(inst), jag_reg2(inst)); |
1093
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parents:
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308 } |
4987fddd42a0
Initial stab at jaguar disassemler
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parents:
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309 } |
4987fddd42a0
Initial stab at jaguar disassemler
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310 } |