Mercurial > repos > blastem
annotate vdp.h @ 450:3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 01 Sep 2013 12:11:28 -0700 |
parents | afbea09d7fb4 |
children | b7c3b2d22858 |
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1 #ifndef VDP_H_ |
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2 #define VDP_H_ |
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3 |
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4 #include <stdint.h> |
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5 #include <stdio.h> |
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6 |
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7 #define VDP_REGS 24 |
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8 #define CRAM_SIZE 64 |
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9 #define VSRAM_SIZE 40 |
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10 #define VRAM_SIZE (64*1024) |
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11 #define LINEBUF_SIZE 320 |
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12 #define FRAMEBUF_ENTRIES (320+27)*(240+27) //PAL active display + full border |
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13 #define MAX_DRAWS 40 |
37 | 14 #define MAX_DRAWS_H32 32 |
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15 #define MAX_SPRITES_LINE 20 |
37 | 16 #define MAX_SPRITES_LINE_H32 16 |
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17 #define MAX_SPRITES_FRAME 80 |
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18 #define MAX_SPRITES_FRAME_H32 64 |
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19 |
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20 #define FBUF_SHADOW 0x0001 |
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21 #define FBUF_HILIGHT 0x0010 |
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22 #define DBG_SHADOW 0x10 |
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23 #define DBG_HILIGHT 0x20 |
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24 #define DBG_PRIORITY 0x8 |
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25 #define DBG_SRC_MASK 0x7 |
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26 #define DBG_SRC_A 0x1 |
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27 #define DBG_SRC_W 0x2 |
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28 #define DBG_SRC_B 0x3 |
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29 #define DBG_SRC_S 0x4 |
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30 #define DBG_SRC_BG 0x0 |
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31 |
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32 #define MCLKS_LINE 3420 |
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33 |
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34 #define FLAG_DOT_OFLOW 0x01 |
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35 #define FLAG_CAN_MASK 0x02 |
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36 #define FLAG_MASKED 0x04 |
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37 #define FLAG_WINDOW 0x08 |
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38 #define FLAG_PENDING 0x10 |
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39 #define FLAG_UNUSED_SLOT 0x20 |
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40 #define FLAG_DMA_RUN 0x40 |
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41 #define FLAG_DMA_PROG 0x80 |
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42 |
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43 #define FLAG2_VINT_PENDING 0x01 |
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44 #define FLAG2_HINT_PENDING 0x02 |
75 | 45 |
46 #define DISPLAY_ENABLE 0x40 | |
47 | |
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48 enum { |
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49 REG_MODE_1=0, |
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50 REG_MODE_2, |
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51 REG_SCROLL_A, |
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52 REG_WINDOW, |
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53 REG_SCROLL_B, |
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54 REG_SAT, |
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55 REG_BG_COLOR=7, |
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56 REG_HINT=0xA, |
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57 REG_MODE_3, |
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58 REG_MODE_4, |
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59 REG_HSCROLL, |
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60 REG_AUTOINC=0xF, |
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61 REG_SCROLL, |
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62 REG_WINDOW_H, |
75 | 63 REG_WINDOW_V, |
64 REG_DMALEN_L, | |
65 REG_DMALEN_H, | |
66 REG_DMASRC_L, | |
67 REG_DMASRC_M, | |
68 REG_DMASRC_H | |
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69 } vdp_regs; |
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70 |
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71 //Mode reg 1 |
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72 #define BIT_HINT_EN 0x10 |
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73 #define BIT_PAL_SEL 0x04 |
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74 #define BIT_HVC_LATCH 0x02 |
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75 #define BIT_DISP_DIS 0x01 |
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76 |
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77 //Mode reg 2 |
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78 #define BIT_DISP_EN 0x40 |
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79 #define BIT_VINT_EN 0x20 |
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80 #define BIT_DMA_ENABLE 0x10 |
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81 #define BIT_PAL 0x08 |
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82 #define BIT_MODE_5 0x04 |
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83 |
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84 //Mode reg 3 |
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85 #define BIT_EINT_EN 0x10 |
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86 #define BIT_VSCROLL 0x04 |
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87 |
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88 //Mode reg 4 |
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89 #define BIT_H40 0x01 |
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90 #define BIT_HILIGHT 0x8 |
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91 #define BIT_DOUBLE_RES 0x4 |
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92 #define BIT_INTERLACE 0x2 |
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93 |
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94 typedef struct { |
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95 uint16_t address; |
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96 int16_t x_pos; |
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97 uint8_t pal_priority; |
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98 uint8_t h_flip; |
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99 } sprite_draw; |
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100 |
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101 typedef struct { |
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102 uint8_t size; |
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103 uint8_t index; |
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104 int16_t y; |
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105 } sprite_info; |
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106 |
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107 typedef struct { |
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108 uint32_t cycle; |
138 | 109 uint16_t address; |
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110 uint16_t value; |
138 | 111 uint8_t cd; |
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112 uint8_t partial; |
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113 } fifo_entry; |
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114 |
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115 typedef struct { |
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116 fifo_entry *fifo_cur; |
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117 fifo_entry *fifo_end; |
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118 uint16_t address; |
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119 uint8_t cd; |
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120 uint8_t flags; |
138 | 121 uint8_t regs[VDP_REGS]; |
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122 //cycle count in MCLKs |
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123 uint32_t cycles; |
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124 uint8_t *vdpmem; |
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125 //stores 2-bit palette + 4-bit palette index + priority for current sprite line |
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126 uint8_t *linebuf; |
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127 //stores 12-bit color + shadow/highlight bits |
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128 void *framebuf; |
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129 void *oddbuf; |
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130 void *evenbuf; |
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131 uint16_t cram[CRAM_SIZE]; |
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132 uint32_t colors[CRAM_SIZE*3]; |
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133 uint32_t debugcolors[1 << (3 + 1 + 1 + 1)];//3 bits for source, 1 bit for priority, 1 bit for shadow, 1 bit for hilight |
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134 uint16_t vsram[VSRAM_SIZE]; |
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135 uint8_t latched_mode; |
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136 uint16_t hscroll_a; |
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137 uint16_t hscroll_b; |
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138 uint8_t sprite_index; |
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139 uint8_t sprite_draws; |
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140 int8_t slot_counter; |
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141 int8_t cur_slot; |
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142 sprite_draw sprite_draw_list[MAX_DRAWS]; |
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143 sprite_info sprite_info_list[MAX_SPRITES_LINE]; |
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144 uint16_t col_1; |
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145 uint16_t col_2; |
75 | 146 uint16_t dma_val; |
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147 uint8_t v_offset; |
131
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148 uint8_t dma_cd; |
317
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149 uint8_t hint_counter; |
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150 uint8_t flags2; |
413
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Initial work on interlace
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151 uint8_t double_res; |
426
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Mike Pavone <pavone@retrodev.com>
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152 uint8_t b32; |
436
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Implement the scroll ring buffer properly without memcpy
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153 uint8_t buf_a_off; |
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154 uint8_t buf_b_off; |
437
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155 uint8_t debug; |
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156 uint8_t *tmp_buf_a; |
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157 uint8_t *tmp_buf_b; |
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158 } vdp_context; |
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159 |
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160 void init_vdp_context(vdp_context * context); |
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161 void vdp_run_context(vdp_context * context, uint32_t target_cycles); |
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162 //runs from current cycle count to VBLANK for the current mode, returns ending cycle count |
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163 uint32_t vdp_run_to_vblank(vdp_context * context); |
75 | 164 //runs until the target cycle is reached or the current DMA operation has completed, whicever comes first |
165 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles); | |
424
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166 uint8_t vdp_load_gst(vdp_context * context, FILE * state_file); |
56
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Fix CRAM and possibly VSRAM writes
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167 void vdp_save_state(vdp_context * context, FILE * outfile); |
75 | 168 int vdp_control_port_write(vdp_context * context, uint16_t value); |
149
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169 int vdp_data_port_write(vdp_context * context, uint16_t value); |
54
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170 uint16_t vdp_control_port_read(vdp_context * context); |
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171 uint16_t vdp_data_port_read(vdp_context * context); |
137 | 172 uint16_t vdp_hv_counter_read(vdp_context * context); |
65
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173 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction); |
317
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174 uint32_t vdp_next_hint(vdp_context * context); |
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175 uint32_t vdp_next_vint(vdp_context * context); |
333 | 176 uint32_t vdp_next_vint_z80(vdp_context * context); |
317
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177 void vdp_int_ack(vdp_context * context, uint16_t int_num); |
322
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178 void vdp_print_sprite_table(vdp_context * context); |
327
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Added some basic VDP debugging features to debugger. Fixed DMA enable bug
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179 void vdp_print_reg_explain(vdp_context * context); |
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180 |
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181 #endif //VDP_H_ |