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changeset 138:aa3e1bb338c9

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Fix VDP reads
author Mike Pavone <pavone@retrodev.com>
date Mon, 31 Dec 2012 11:26:57 -0800
parents 0e7e1ccc0a81
children cce22fb4c450
files runtime.S vdp.c vdp.h
diffstat 3 files changed, 26 insertions(+), 13 deletions(-) [+]
line wrap: on
line diff
--- a/runtime.S	Sun Dec 30 22:39:41 2012 -0800
+++ b/runtime.S	Mon Dec 31 11:26:57 2012 -0800
@@ -215,15 +215,22 @@
 	/* bail out if fifo is full */
 	je fifo_fallback
 	/* populate FIFO entry */
-	mov %cx, 4(%rbx) /* value */
-	movb $0, 6(%rbx) /* partial */
+	mov %cx, 6(%rbx) /* value */
+	mov 16(%rdx), %cx
+	mov %cx, 4(%rbx) /* address */
+	mov 18(%rdx), %cl
+	mov %cl, 8(%rbx) /* cd */
+	movb $0, 9(%rbx) /* partial */
 	mov %eax, %ecx
 	shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
 	sub %eax, %ecx
 	mov %ecx, (%rbx) /* cycle */
 	/* update fifo_cur and store back in 68K context */
-	add $8, %rbx
+	add $12, %rbx
 	mov %rbx, (%rdx)
+	/* update address register */
+	movzbw 35(%rdx), %bx
+	add %bx, 16(%rdx)
 	/* clear pending flag */
 	andb $0xEF, 19(%rdx)
 	pop %rbx
--- a/vdp.c	Sun Dec 30 22:39:41 2012 -0800
+++ b/vdp.c	Mon Dec 31 11:26:57 2012 -0800
@@ -299,17 +299,18 @@
 			if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) {
 				context->flags |= FLAG_DMA_RUN;
 				context->dma_val = start->value;
+				context->address = start->address; //undo auto-increment
 				context->dma_cd = context->cd;
 			} else {
-				switch (context->cd & 0xF)
+				switch (start->cd & 0xF)
 				{
 				case VRAM_WRITE:
 					if (start->partial) {
 						//printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1);
-						context->vdpmem[context->address ^ 1] = start->value;
+						context->vdpmem[start->address ^ 1] = start->value;
 					} else {
 						//printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address);
-						context->vdpmem[context->address] = start->value >> 8;
+						context->vdpmem[start->address] = start->value >> 8;
 						start->partial = 1;
 						//skip auto-increment and removal of entry from fifo
 						return;
@@ -317,16 +318,16 @@
 					break;
 				case CRAM_WRITE:
 					//printf("CRAM Write: %X to %X\n", start->value, context->address);
-					context->cram[(context->address/2) & (CRAM_SIZE-1)] = start->value;
+					context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value;
 					break;
 				case VSRAM_WRITE:
-					if (((context->address/2) & 63) < VSRAM_SIZE) {
+					if (((start->address/2) & 63) < VSRAM_SIZE) {
 						//printf("VSRAM Write: %X to %X\n", start->value, context->address);
-						context->vsram[(context->address/2) & 63] = start->value;
+						context->vsram[(start->address/2) & 63] = start->value;
 					}
 					break;
 				}
-				context->address += context->regs[REG_AUTOINC];
+				//context->address += context->regs[REG_AUTOINC];
 			}
 			fifo_entry * cur = start+1;
 			if (cur < context->fifo_cur) {
@@ -1074,9 +1075,12 @@
 		vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
 	}
 	context->fifo_cur->cycle = context->cycles;
+	context->fifo_cur->address = context->address;
 	context->fifo_cur->value = value;
+	context->fifo_cur->cd = context->cd;
 	context->fifo_cur->partial = 0;
 	context->fifo_cur++;
+	context->address += context->regs[REG_AUTOINC];
 }
 
 uint16_t vdp_control_port_read(vdp_context * context)
@@ -1103,7 +1107,7 @@
 uint16_t vdp_data_port_read(vdp_context * context)
 {
 	context->flags &= ~FLAG_PENDING;
-	if (!(context->cd & 1)) {
+	if (context->cd & 1) {
 		return 0;
 	}
 	//Not sure if the FIFO should be drained before processing a read or not, but it would make sense
@@ -1112,7 +1116,7 @@
 		vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
 	}
 	uint16_t value = 0;
-	switch (context->cd & 0x7)
+	switch (context->cd & 0xF)
 	{
 	case VRAM_READ:
 		value = context->vdpmem[context->address] << 8;
--- a/vdp.h	Sun Dec 30 22:39:41 2012 -0800
+++ b/vdp.h	Mon Dec 31 11:26:57 2012 -0800
@@ -77,7 +77,9 @@
 
 typedef struct {
 	uint32_t cycle;
+	uint16_t address;
 	uint16_t value;
+	uint8_t  cd;
 	uint8_t  partial;
 } fifo_entry;
 
@@ -87,6 +89,7 @@
 	uint16_t    address;
 	uint8_t     cd;
 	uint8_t	    flags;
+	uint8_t     regs[VDP_REGS];
 	//cycle count in MCLKs
 	uint32_t    cycles;
 	uint8_t     *vdpmem;
@@ -103,7 +106,6 @@
 	uint8_t     sprite_draws;
 	int8_t      slot_counter;
 	int8_t      cur_slot;
-	uint8_t     regs[VDP_REGS];
 	sprite_draw sprite_draw_list[MAX_DRAWS];
 	sprite_info sprite_info_list[MAX_SPRITES_LINE];
 	uint16_t    col_1;