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M68K to x86 translation works for a limited subset of instructions and addressing modes
author Mike Pavone <pavone@retrodev.com>
date Tue, 04 Dec 2012 19:13:12 -0800
parents de0085d4ea40
children 44e661913a51
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de0085d4ea40 Add asssembly runtime code stub
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2 .global handle_cycle_limit
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3 handle_cycle_limit:
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4 ret
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5
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6 .global m68k_write_word
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7 m68k_write_word:
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8 and $0xFFFFFF, %rdi
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9 cmp $0x400000, %edi
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10 jle cart_w
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11 cmp $0xE00000, %edi
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12 jge workram_w
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13 jmp inccycles
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14 workram_w:
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15 and $0xFFFF, %rdi
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16 mov %cx, (%r9, %rdi)
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17 jmp inccycles
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18 cart_w:
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19 mov %cx, (%r8, %rdi)
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20 jmp inccycles
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21
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22 .global m68k_write_byte
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23 m68k_write_byte:
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24 and $0xFFFFFF, %rdi
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25 /* deal with byte swapping */
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26 xor $1, %edi
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27 cmp $0x400000, %edi
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28 jle cart_wb
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29 cmp $0xE00000, %edi
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30 jge workram_wb
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31 jmp inccycles
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32 workram_wb:
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33 and $0xFFFF, %rdi
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34 mov %cl, (%r9, %rdi)
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35 jmp inccycles
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36 cart_wb:
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37 mov %cl, (%r8, %rdi)
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38 jmp inccycles
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39
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40 .global m68k_write_long_lowfirst
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41 m68k_write_long_lowfirst:
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42 push %rdi
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43 add $2, %edi
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44 call m68k_write_word
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45 shr $16, %ecx
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46 pop %rdi
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47 jmp m68k_write_word
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48
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49 .global m68k_write_long_highfirst
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50 m68k_write_long_highfirst:
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51 push %rdi
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52 push %rcx
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53 shr $16, %ecx
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54 call m68k_write_word
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55 pop %rcx
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56 pop %rdi
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57 add $2, %rdi
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58 jmp m68k_write_word
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de0085d4ea40 Add asssembly runtime code stub
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59
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60 .global m68k_read_word_scratch1
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61 m68k_read_word_scratch1:
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62 and $0xFFFFFF, %rcx
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63 cmp $0x400000, %ecx
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64 jle cart
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65 cmp $0xE00000, %ecx
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66 jge workram
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67 xor %cx, %cx
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68 jmp inccycles
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69 workram:
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70 and $0xFFFF, %rcx
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71 mov (%r9, %rcx), %cx
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72 jmp inccycles
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73 cart:
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74 mov (%r8, %rcx), %cx
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75 inccycles:
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76 add $4, %rax
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77 cmp %rbp, %rax
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78 jge sync
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79 ret
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80 sync:
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81 ret
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82
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83 .global m68k_read_long_scratch1
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84 m68k_read_long_scratch1:
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85 push %rcx
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86 call m68k_read_word_scratch1
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87 mov %cx, %di
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88 pop %rcx
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89 add $2, %ecx
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90 call m68k_read_word_scratch1
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91 and $0xFFFF, %ecx
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92 shl $16, %edi
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93 or %edi, %ecx
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94 ret
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95
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96 .global m68k_read_byte_scratch1
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97 m68k_read_byte_scratch1:
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98 and $0xFFFFFF, %rcx
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99 /* deal with byte swapping */
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100 xor $1, %ecx
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101 cmp $0x400000, %ecx
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102 jle cart_b
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103 cmp $0xE00000, %ecx
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104 jge workram_b
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105 xor %cl, %cl
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106 jmp inccycles
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107 workram_b:
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108 and $0xFFFF, %rcx
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109 mov (%r9, %rcx), %cl
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110 jmp inccycles
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111 cart_b:
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112 mov (%r8, %rcx), %cl
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113 jmp inccycles
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114
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115 ret_addr_msg:
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116 .asciz "Program modified return address on stack: found %X, expected %X\n"
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117
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118 .global m68k_modified_ret_addr
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119 m68k_modified_ret_addr:
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120 lea ret_addr_msg(%rip), %rdi
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121 mov %rcx, %rsi
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122 mov 8(%rsp), %rdx
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123 call printf
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124 mov $1, %rdi
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125 call exit
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126
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127 .global m68k_save_context
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128 m68k_save_context:
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parents: 17
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129 mov %bl, 1(%rsi) /* N Flag */
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parents: 17
diff changeset
130 mov %bh, 2(%rsi) /* V flag */
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parents: 17
diff changeset
131 mov %dl, 3(%rsi) /* Z flag */
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parents: 17
diff changeset
132 mov %dh, 4(%rsi) /* C flag */
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parents: 17
diff changeset
133 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
134 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
135 mov %r12d, 16(%rsi) /* d2 */
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parents: 17
diff changeset
136 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
137 mov %r14d, 44(%rsi) /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
138 mov %r15d, 68(%rsi) /* a7 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
139 ret
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parents: 17
diff changeset
140
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parents: 17
diff changeset
141 .global m68k_load_context
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parents: 17
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142 m68k_load_context:
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parents: 17
diff changeset
143 mov 1(%rsi), %bl /* N Flag */
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parents: 17
diff changeset
144 mov 2(%rsi), %bh /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
145 mov 3(%rsi), %dl /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
146 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
147 mov 8(%rsi), %r10d /* d0 */
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parents: 17
diff changeset
148 mov 12(%rsi), %r11d /* d1 */
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parents: 17
diff changeset
149 mov 16(%rsi), %r12d /* d2 */
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parents: 17
diff changeset
150 mov 40(%rsi), %r13d /* a0 */
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parents: 17
diff changeset
151 mov 44(%rsi), %r14d /* a1 */
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parents: 17
diff changeset
152 mov 68(%rsi), %r15d /* a7 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
153 mov 72(%rsi), %ebp /* target cycle count */
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parents: 17
diff changeset
154 mov 76(%rsi), %eax /* current cycle count */
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parents: 17
diff changeset
155 mov 80(%rsi), %r8d /* cartridge address */
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parents: 17
diff changeset
156 mov 88(%rsi), %r9d /* work ram address */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
157 ret
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parents: 17
diff changeset
158
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parents: 17
diff changeset
159 .global m68k_start_context
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parents: 17
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160 m68k_start_context:
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parents: 17
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161 call m68k_load_context
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parents: 17
diff changeset
162 jmp *%rdi