repos/blastem: m68k_to_x86.c annotate

annotate m68k_to_x86.c @ 67:534eb4976423

Fix BTST

author	Mike Pavone <pavone@retrodev.com>
date	Thu, 20 Dec 2012 00:56:33 -0800
parents	7a22a0e6c004
children	cebd0b5ac7f0

rev	line source
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "m68k_to_x86.h"
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3 #include <stdio.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4 #include <stddef.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	5 #include <stdlib.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	6 #include <string.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	7
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #define BUS 4
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	9 #define PREDEC_PENALTY 2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 #define CYCLES RAX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define LIMIT RBP
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	12 #define SCRATCH1 RCX
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	13 #define SCRATCH2 RDI
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define CONTEXT RSI
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define FLAG_N RBX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define FLAG_V BH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define FLAG_Z RDX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define FLAG_C DH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 typedef struct {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 int32_t disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 uint8_t mode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 uint8_t base;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 uint8_t index;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 uint8_t cycles;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 } x86_ea;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 void handle_cycle_limit();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	30 void m68k_read_word_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	31 void m68k_read_long_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	32 void m68k_read_byte_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	33 void m68k_write_word();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	34 void m68k_write_long_lowfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	35 void m68k_write_long_highfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	36 void m68k_write_byte();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	37 void m68k_save_context();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	38 void m68k_modified_ret_addr();
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	39 void m68k_native_addr();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	40 void m68k_start_context(uint8_t * addr, m68k_context * context);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	41
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 uint8_t * cycles(uint8_t * dst, uint32_t num)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	44 dst = add_ir(dst, num, CYCLES, SZ_D);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	46
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 if (op->addr_mode == MODE_REG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 return opts->dregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 if (op->addr_mode == MODE_AREG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 return opts->aregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 return -1;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	57
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	58 //must be called with an m68k_op_info that uses a register
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	59 size_t reg_offset(m68k_op_info *op)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	60 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	61 if (op->addr_mode == MODE_REG) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	62 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	63 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	64 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	65 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	66
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	67 void print_regs_exit(m68k_context * context)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	69 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	70 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	71 printf("d%d: %X\n", i, context->dregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	72 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	73 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	74 printf("a%d: %X\n", i, context->aregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	75 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	76 exit(0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	77 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	78
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	79 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	80 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	81 int8_t reg = native_reg(&(inst->src), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	82 int32_t dec_amount,inc_amount;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 if (reg >= 0) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	84 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	85 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	86 return out;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	88 switch (inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	89 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	90 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	91 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	92 //We only get one memory parameter, so if the dst operand is a register in memory,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	93 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	94 reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	95 if (reg >= 0 \|\| inst->dst.addr_mode == MODE_UNUSED \|\| (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	96 \|\| inst->op == M68K_EXG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	97
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	98 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	99 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	100 ea->disp = reg_offset(&(inst->src));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	101 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	102 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	103 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	104 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	105 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	106 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	107 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	108 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	109 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	110 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	111 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	112 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	113 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	114 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	115 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	116 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	117 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	118 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	119 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	120 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	121 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	122 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	123 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	124 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	125 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	126 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	127 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	128 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	129 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	130 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	131 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	132 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	133 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	134
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	135 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	136 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	137 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	138 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	139 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	140 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	141 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	142 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	143 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	144 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	145 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	146 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	147 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	148 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	149 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	150 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	151 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	152 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	153 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	154 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	155 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	156 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	157 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	158 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	159 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	160 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	161 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	162 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	163 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	164 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	165 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	166 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	167 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	168 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	169 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	170 case MODE_IMMEDIATE_WORD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	171 if (inst->variant != VAR_QUICK) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	172 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	173 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	174 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	175 ea->disp = inst->src.params.immed;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	176 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	177 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	178 printf("address mode %d not implemented (src)\n", inst->src.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	179 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	180 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	181 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	182 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	183
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	184 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	185 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	186 int8_t reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	187 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	188 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	189 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	190 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	191 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	192 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	193 switch (inst->dst.addr_mode)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 case MODE_AREG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	197 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	198 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	199 ea->disp = reg_offset(&(inst->dst));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	200 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	201 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	202 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	203 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	204 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	205 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	206 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	207 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	208 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	209 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	210 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	211 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	212 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	213 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	214 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	215 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	216 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	217 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	218 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	219 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	220 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	221 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	222 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	223 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	224 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	225 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	226 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	227 //save reg value in SCRATCH2 so we can use it to save the result in memory later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	228 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	229 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	230 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	231 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	232 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	233
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	234 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	235 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	236 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	237 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	238 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	239 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	240 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	241 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	242 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	243 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	244 break;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	245 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	246 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	247 //Add cycles for reading address from instruction stream
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	248 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	249 out = cycles(out, BUS*2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	250 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	251 out = cycles(out, BUS);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	252 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	253 out = mov_ir(out, inst->dst.params.immed, SCRATCH1, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	254 out = push_r(out, SCRATCH1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	255 switch (inst->extra.size)
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	256 {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	257 case OPSIZE_BYTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	258 out = call(out, (char *)m68k_read_byte_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	259 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	260 case OPSIZE_WORD:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	261 out = call(out, (char *)m68k_read_word_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	262 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	263 case OPSIZE_LONG:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	264 out = call(out, (char *)m68k_read_long_scratch1);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	265 break;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	266 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	267 out = pop_r(out, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	268 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	269 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	270 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	271 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	272 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	273 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	274 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	275 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	276 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	277
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	278 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	279 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	280 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	281 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	282 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	283 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	284 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	285 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	286 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	287 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	288 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	289 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	290 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	291 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	292 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	293 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	294 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	295 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	296
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	297 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	298 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	299 address &= 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	300 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	301 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	302 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	303 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	304 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	305 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	306 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	307 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	308 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	309 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	310
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	311 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	312 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	313 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	314 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	315 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	316 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	317 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	318 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	319
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	320 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	321 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	322 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	323 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	324 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	325 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	326 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	327 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	328 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	329 printf("Native dest: %p, Offset address: %p, displacement: %X\n", native, cur->dest, disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	330 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	331 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	332 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	333 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	334 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	335 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	336 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	337 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	338 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	339 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	340 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	341 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	342 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	343 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	344 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	345 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	346 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	347
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	348 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	349 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	350 //FIXME: This probably isn't going to work with real code in a lot of cases, no guarantee that
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	351 //all the code in 1KB block is going to be translated at the same time
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	352 address &= 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	353 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	354 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	355 native_code_map[chunk].base = native_addr;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	356 native_code_map[chunk].offsets = malloc(sizeof(uint16_t) * NATIVE_CHUNK_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	357 memset(native_code_map[chunk].offsets, 0xFF, sizeof(uint16_t) * NATIVE_CHUNK_SIZE);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	358 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	359 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	360 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	361 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	362
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	363 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	364 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	365 int8_t reg, flags_reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	366 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	367 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	368 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	369 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	370 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	371 reg = native_reg(&(inst->dst), opts);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	372 //update statically set flags
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	373 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	374 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	375
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	376 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	377 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	378 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	379 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	380 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	381 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	382 printf("moving %d to temp register %d\n", src.disp, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	383 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	384 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	385 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	386 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	387 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	388 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	389 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	390 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	391 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	392 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	393 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	394 dst = mov_rr(dst, src.base, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	395 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	396 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	397 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	398 dst = mov_ir(dst, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	399 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	400 } else if(src.mode == MODE_REG_DIRECT) {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	401 printf("mov_rrdisp8 from reg %d to offset %d from reg %d (%d)\n", src.base, (int)reg_offset(&(inst->dst)), CONTEXT, inst->dst.params.regs.pri);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	402 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	403 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	404 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	405 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	406 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	407 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	408 dst = setcc_r(dst, CC_S, FLAG_N);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	409 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	410 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	411 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	412 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	413 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	414 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	415 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	416 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 case MODE_AREG_INDIRECT:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	418 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	419 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	420 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	421 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	422 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	423 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	424 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	425 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	426 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	427 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	428 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	429 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	430 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	431 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	432 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	433 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	434 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	435 dst = setcc_r(dst, CC_S, FLAG_N);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	436 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	437 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	438 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	439 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	440 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	441 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	442 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	443 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	444 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	445 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	446 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	447 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	448 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	449 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	450 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	451 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	452 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	453 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	454 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	455 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	456 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	457 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	458 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	459 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	460 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	461 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	462 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	463 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	464 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	465 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	466 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	467 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	468 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	469 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	470 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	471 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	472 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	473 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	474 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	475 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	476 dst = setcc_r(dst, CC_S, FLAG_N);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	477 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	478 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	479 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	480 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	481 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	482 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	483 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	484 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	485 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	486 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	487 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	488 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	489 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	490 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	491 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	492 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	493 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	494
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	495 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	496 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	497 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	498 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	499
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	500 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	501 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	502 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	503 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	504 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	505 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	506 uint8_t reg = native_reg(&(inst->dst), opts);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	507 if (reg >= 0) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	508 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	509 return xor_rr(dst, reg, reg, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	510 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	511 int32_t dec_amount,inc_amount;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	512 switch (inst->dst.addr_mode)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	513 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	514 case MODE_REG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	515 case MODE_AREG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	516 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	517 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	518 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	519 case MODE_AREG_PREDEC:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	520 dst = cycles(dst, PREDEC_PENALTY);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	521 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	522 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	523 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	524 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	525 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	526 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	527 case MODE_AREG_INDIRECT:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	528 case MODE_AREG_POSTINC:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	529 //add cycles for prefetch and wasted read
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	530 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8));
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	531 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	532 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	533 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	534 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	535 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	536 dst = xor_rr(dst, SCRATCH1, SCRATCH1, SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	537 switch (inst->extra.size)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	538 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	539 case OPSIZE_BYTE:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	540 dst = call(dst, (char *)m68k_write_byte);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	541 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	542 case OPSIZE_WORD:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	543 dst = call(dst, (char *)m68k_write_word);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	544 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	545 case OPSIZE_LONG:
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	546 dst = call(dst, (char *)m68k_write_long_highfirst);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	547 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	548 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	549 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	550 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	551 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	552 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	553 } else {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	554 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	555 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	556 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	557 break;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	558 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	559 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	560 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	561
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	562 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	563 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	564 int8_t dst_reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	565 switch(inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	566 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	567 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	568 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	569 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	570 if (dst_reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	571 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	572 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	573 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	574 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	575 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	576 if (dst_reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	577 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	578 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	579 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	580 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	581 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	582 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	583 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	584 case MODE_ABSOLUTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	585 case MODE_ABSOLUTE_SHORT:
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	586 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	587 if (dst_reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	588 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	589 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	590 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	591 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	592 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	593 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	594 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	595 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	596
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	597 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	598 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	599 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	600 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	601 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	602 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	603 dst = push_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	604 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	605 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	606 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	607 printf("bsr@%X: after=%X, disp=%X, dest=%X\n", inst->address, after, disp, after+disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	608 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	609 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	610 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	611 //dummy address to be replaced later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	612 dest_addr = dst + 5;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	613 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	614 dst = call(dst, (char *)dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	615 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	616 dst = pop_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	617 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	618 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	619
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	620 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	621 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	622 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	623 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	624 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	625 printf("bcc@%X: after=%X, disp=%X, dest=%X\n", inst->address, after, disp, after+disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	626 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	627 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	628 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	629 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	630 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	631 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	632 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	633 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	634 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	635 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	636 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	637 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	638 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	639 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	640 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	641 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	642 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	643 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	644 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	645 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	646 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	647 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	648 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	649 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	650 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	651 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	652 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	653 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	654 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	655 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	656 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	657 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	658 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	659 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	660 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	662 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	664 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	665 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	666 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	667 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	668 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	669 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	670 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	671 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	672 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	673 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	674 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	675 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	676 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	677 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	678 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	679 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	680 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	681 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	682 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	683 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	684 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	685 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	686
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	687 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	688 {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	689 uint8_t * dest_addr;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	690 switch(inst->src.addr_mode)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	691 {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	692 case MODE_AREG_INDIRECT:
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	693 dst = cycles(dst, BUS);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	694 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	695 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	696 } else {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	697 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	698 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	699 dst = call(dst, (uint8_t *)m68k_native_addr);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	700 //TODO: Finish me
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	701 //TODO: Fix timing
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	702 break;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	703 case MODE_ABSOLUTE:
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	704 case MODE_ABSOLUTE_SHORT:
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	705 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	706 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	707 if (!dest_addr) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	708 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	709 //dummy address to be replaced later, make sure it generates a 4-byte displacement
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	710 dest_addr = dst + 256;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	711 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	712 dst = jmp(dst, dest_addr);
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	713 break;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	714 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	715 return dst;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	716 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	717
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	718 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	719 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	720 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	721 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	722 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	723 dst = call(dst, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	724 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	725 dst = jcc(dst, CC_NZ, dst+3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	726 dst = retn(dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	727 dst = jmp(dst, (char *)m68k_modified_ret_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	728 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	729 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	730
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	731 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	732 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	733 //best case duration
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	734 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	735 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	736 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	737 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	738 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	739 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	740 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	741 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	742 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	743 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	744 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	745 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	746 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	747 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	748 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	749 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	750 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	751 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	752 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	753 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	754 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	755 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	756 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	757 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	758 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	759 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	760 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	761 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	762 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	763 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	764 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	765 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	766 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	767 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	768 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	769 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	770 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	771 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	772 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	773 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	774 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	775 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	776 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	777 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	778 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	779 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	780 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	781 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	782 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	783 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	784 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	785 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	786 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	787 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	788 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	789 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	790 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	791 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	792 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	793 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	794 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	795 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	796 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	797 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	798 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	799 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	800 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	801 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	802 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	803 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	804 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	805 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	806 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	807 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	808 }
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	809 return dst;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	810 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	811
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	812 typedef uint8_t * (shift_ir_t)(uint8_t out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	813 typedef uint8_t * (shift_irdisp8_t)(uint8_t out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	814 typedef uint8_t * (shift_clr_t)(uint8_t out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	815 typedef uint8_t * (shift_clrdisp8_t)(uint8_t out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	816
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	817 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea src_op, x86_ea dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	818 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	819 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	820 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	821 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	822 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	823 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	824 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	825 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	826 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	827 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	828 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	829 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	830 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	831 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	832 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	833 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	834 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	835 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	836 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	837 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	838 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	839 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	840 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	841 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	842 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	843 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	844 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	845 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	846 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	847 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	848 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	849 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	850 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	851 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	852 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	853
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	854 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	855 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	856 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	857 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	858 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	859 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	860 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	861 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	862 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	863 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	864 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	865 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	866 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	867 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	868 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	869 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	870 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	871 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	872 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	873 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	874 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	875 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	876 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	877 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	878 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	879 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	880
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	881 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	882 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	883 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	884 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	885 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	886 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	887 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	888 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	889 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	890
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	891 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	892
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	893 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	894 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	895 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	896 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	897 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	898 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	899 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	900 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	901 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	902 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	903 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	904 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	905 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	906 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	907 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	908 }
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	909 return dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	910 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	911
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	912 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	913 {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	914 uint8_t * end_off;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	915 map_native_address(opts->native_code_map, inst->address, dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	916 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	917 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	918 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	919 return translate_m68k_lea(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	920 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	921 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	922 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	923 return translate_m68k_bcc(dst, inst, opts);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	924 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	925 return translate_m68k_jmp(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	926 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	927 return translate_m68k_rts(dst, inst, opts);
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	928 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	929 return translate_m68k_dbcc(dst, inst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	930 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	931 return translate_m68k_clr(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	932 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	933 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	934 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	935 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	936 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	937 if (inst->dst.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	938 dst = translate_m68k_dst(inst, &dst_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	939 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	940 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	941 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	942 case M68K_ABCD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	943 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	944 case M68K_ADD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	945 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	946 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	947 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	948 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	949 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	950 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	951 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	952 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	953 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	954 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	955 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	956 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	957 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	958 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	959 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	960 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	961 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	962 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	963 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	964 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	965 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	966 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	967 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	968 case M68K_ADDX:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	969 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	970 case M68K_AND:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	971 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	972 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	973 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	974 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	975 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	976 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	977 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	978 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	979 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	980 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	981 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	982 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	983 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	984 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	985 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	986 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	987 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	988 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	989 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	990 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	991 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	992 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	993 case M68K_ANDI_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	994 case M68K_ANDI_SR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	995 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	996 case M68K_ASL:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	997 case M68K_LSL:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	998 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	999 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1000 case M68K_ASR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1001 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1002 break;
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1003 case M68K_LSR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1004 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1005 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1006 case M68K_BCHG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1007 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1008 case M68K_BSET:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1009 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1010 case M68K_BTST:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1011 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67 534eb4976423 Fix BTST Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	1012 if (src_op.mode == MODE_IMMED) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1013 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1014 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1015 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1016 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1017 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1018 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1019 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1020 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1021 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1022 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1023 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1024 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1025 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1026 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1027 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1028 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1029 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1030 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1031 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1032 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1033 dst = and_ir(dst, 0x7, src_op.base, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1034 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1035 if (dst_op.mode == MODE_REG_DIRECT) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1036 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1037 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1038 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1039 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1040 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1041 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1042 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1043 dst = setcc_r(dst, CC_NC, FLAG_Z);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1044 if (src_op.base == SCRATCH2) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1045 dst = pop_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1046 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	1047 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1048 case M68K_CHK:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1049 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1050 case M68K_CMP:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1051 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1052 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1053 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1054 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1055 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1056 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1057 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1058 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1059 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1060 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1061 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1062 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1063 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1064 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1065 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1066 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1067 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1068 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1069 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1070 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1071 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1072 case M68K_DIVS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1073 case M68K_DIVU:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1074 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1075 case M68K_EOR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1076 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1077 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1078 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1079 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1080 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1081 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1082 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1083 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1084 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1085 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1086 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1087 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1088 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1089 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1090 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1091 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1092 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1093 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1094 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1095 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1096 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1097 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1098 case M68K_EORI_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1099 case M68K_EORI_SR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1100 case M68K_EXG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1101 dst = cycles(dst, 6);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1102 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1103 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1104 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1105 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1106 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1107 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1108 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1109 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1110 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1111 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1112 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1113 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1114 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1115 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1116 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1117 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1118 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1119 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1120 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1121 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1122 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1123 case M68K_EXT:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1124 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1125 case M68K_ILLEGAL:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1126 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1127 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1128 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1129 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1130 case M68K_JSR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1131 case M68K_LEA:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1132 case M68K_LINK:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1133 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1134 case M68K_MOVE_FROM_SR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1135 case M68K_MOVE_SR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1136 case M68K_MOVE_USP:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1137 case M68K_MOVEM:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1138 case M68K_MOVEP:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1139 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1140 case M68K_MULU:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1141 case M68K_NBCD:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1142 case M68K_NEG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1143 case M68K_NEGX:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1144 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1145 case M68K_NOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1146 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1147 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1148 case M68K_NOT:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1149 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1150 case M68K_OR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1151 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1152 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1153 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1154 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1155 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1156 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1157 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1158 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1159 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1160 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1161 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1162 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1163 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1164 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1165 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1166 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1167 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1168 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1169 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1170 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1171 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1172 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1173 case M68K_ORI_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1174 case M68K_ORI_SR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1175 case M68K_PEA:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1176 case M68K_RESET:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1177 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1178 case M68K_ROR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1179 case M68K_ROXL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1180 case M68K_ROXR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1181 case M68K_RTE:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1182 case M68K_RTR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1183 case M68K_SBCD:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1184 case M68K_SCC:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1185 case M68K_STOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1186 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1187 case M68K_SUB:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1188 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1189 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1190 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1191 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1192 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1193 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1194 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1195 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1196 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1197 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1198 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1199 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1200 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1201 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1202 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1203 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1204 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1205 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1206 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1207 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1208 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1209 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1210 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1211 case M68K_SUBX:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1212 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1213 case M68K_SWAP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1214 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1215 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1216 dst = rol_ir(dst, 16, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1217 } else{
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1218 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1219 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1220 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1221 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1222 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1223 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1224 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1225 case M68K_TAS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1226 case M68K_TRAP:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1227 case M68K_TRAPV:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1228 case M68K_TST:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1229 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1230 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1231 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1232 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1233 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1234 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1235 dst = setcc_r(dst, CC_C, FLAG_C);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1236 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1237 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1238 dst = setcc_r(dst, CC_O, FLAG_V);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	1239 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1240 case M68K_UNLK:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1241 case M68K_INVALID:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1242 break;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1243 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1244 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1245 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1246
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1247 uint8_t * translate_m68k_stream(uint8_t * dst, uint8_t * dst_end, uint32_t address, m68k_context * context)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1248 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1249 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1250 x86_68k_options * opts = context->options;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1251 char disbuf[1024];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1252 uint16_t encoded = context->mem_pointers[0] + address/2, next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1253 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1254 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1255 if (dst_end-dst < 128) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1256 puts("out of code memory");
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1257 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1258 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1259 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1260 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1261 encoded = next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1262 m68k_disasm(&instbuf, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1263 printf("%X: %s\n", instbuf.address, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1264 dst = translate_m68k(dst, &instbuf, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1265 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1266 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1267 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1268 address = opts->deferred->address;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1269 encoded = context->mem_pointers[0] + address/2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1270 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1271 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1272 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1273 } while(encoded != NULL);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1274 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1275 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1276
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1277 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1278 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1279 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1280 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1281 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1282
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1283 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1284 {
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1285 //TODO: Make this actually use the normal read functions
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1286 context->aregs[7] = context->mem_pointers[0][0] << 16 \| context->mem_pointers[0][1];
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1287 uint32_t address = context->mem_pointers[0][2] << 16 \| context->mem_pointers[0][3];
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1288 start_68k_context(context, address);
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1289 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	1290
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1291 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1292 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1293 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1294 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1295 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1296 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1297 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1298 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1299 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1300 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1301 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1302 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1303 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1304 opts->deferred = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1305 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1306
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1307 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1308 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1309 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1310 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1311 context->options = opts;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1312 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1313

Mercurial > repos > blastem

annotate m68k_to_x86.c @ 67:534eb4976423