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annotate runtime.S @ 60:6ffea8607730

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Fix operand order for AND instructions
author Mike Pavone <pavone@retrodev.com>
date Tue, 18 Dec 2012 23:55:10 -0800
parents 32650c77008a
children 2b1a65f4b85d
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
17
de0085d4ea40 Add asssembly runtime code stub
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1
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2 .global handle_cycle_limit
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3 handle_cycle_limit:
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4 call m68k_save_context
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5 mov %rsi, %rdi
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6 call sync_components
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7 mov %rax, %rsi
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8 call m68k_load_context
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9 ret
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10
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11 do_vdp_port_write:
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12 call m68k_save_context
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13 mov %rcx, %rdx
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14 call vdp_port_write
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15 mov %rax, %rsi
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16 call m68k_load_context
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17 ret
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18
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19 do_vdp_port_read:
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20 mov %ecx, %edi
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21 call m68k_save_context
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22 call vdp_port_read
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23 mov %rax, %rsi
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24 call m68k_load_context
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25 mov 120(%rsi), %cx
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26 ret
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27
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28 bad_access_msg:
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29 .asciz "Program tried to access illegal 68K address %X\n"
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31 .global m68k_write_word
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32 .global try_fifo_write
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33 m68k_write_word:
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34 and $0xFFFFFF, %rdi
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35 cmp $0x400000, %edi
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36 jle cart_w
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37 cmp $0xE00000, %edi
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38 jge workram_w
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39 cmp $0xC00000, %edi
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40 jge vdp_psg_w
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41 jmp inccycles
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42 workram_w:
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43 and $0xFFFF, %rdi
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44 mov %cx, (%r9, %rdi)
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45 jmp inccycles
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46 cart_w:
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47 mov %cx, (%r8, %rdi)
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48 jmp inccycles
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49 vdp_psg_w:
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50 test $0x2700E0, %edi
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51 jnz crash
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52 and $0x1F, %edi
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53 cmp $4, %edi
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54 jl try_fifo_write
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55 jmp do_vdp_port_write
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56 try_fifo_write:
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57 push %rdx
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58 push %rbx
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59 /* fetch VDP context pointer from 68K context */
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60 mov 112(%rsi), %rdx
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61 /* get fifo_cur and compare it to fifo_end */
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62 mov (%rdx), %rbx
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63 cmp %rbx, 8(%rdx)
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64 /* bail out if fifo is full */
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65 je fifo_fallback
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66 /* populate FIFO entry */
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67 mov %cx, 4(%rbx) /* value */
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68 movb $0, 6(%rbx) /* partial */
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69 mov %eax, %ecx
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70 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
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71 sub %eax, %ecx
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72 mov %ecx, (%rbx) /* cycle */
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73 /* update fifo_cur and store back in 68K context */
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74 add $8, %rbx
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75 mov %rbx, (%rdx)
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76 /* clear pending flag */
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77 andb $0xEF, 19(%rdx)
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78 pop %rbx
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79 pop %rdx
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80 jmp inccycles
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81 fifo_fallback:
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82 pop %rbx
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83 pop %rdx
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84 jmp do_vdp_port_write
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85 crash:
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86 mov %edi, %esi
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87 lea bad_access_msg(%rip), %rdi
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88 call printf
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89 mov $1, %rdi
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90 call exit
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91
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92 .global m68k_write_byte
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93 m68k_write_byte:
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94 and $0xFFFFFF, %rdi
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95 /* deal with byte swapping */
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96 xor $1, %edi
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97 cmp $0x400000, %edi
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98 jle cart_wb
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99 cmp $0xE00000, %edi
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100 jge workram_wb
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101 jmp inccycles
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102 workram_wb:
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103 and $0xFFFF, %rdi
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104 mov %cl, (%r9, %rdi)
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105 jmp inccycles
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106 cart_wb:
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107 mov %cl, (%r8, %rdi)
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108 jmp inccycles
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109
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110 .global m68k_write_long_lowfirst
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111 m68k_write_long_lowfirst:
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112 push %rdi
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113 add $2, %edi
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114 call m68k_write_word
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115 shr $16, %ecx
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116 pop %rdi
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117 jmp m68k_write_word
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118
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119 .global m68k_write_long_highfirst
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120 m68k_write_long_highfirst:
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121 push %rdi
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122 push %rcx
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123 shr $16, %ecx
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124 call m68k_write_word
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125 pop %rcx
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126 pop %rdi
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127 add $2, %rdi
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128 jmp m68k_write_word
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129
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130 .global m68k_read_word_scratch1
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131 m68k_read_word_scratch1:
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132 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
133 cmp $0x400000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
134 jle cart
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
135 cmp $0xE00000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
136 jge workram
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
137 cmp $0xC00000, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
138 jge vdp_psg
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
139 xor %cx, %cx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
140 dec %cx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
141 jmp inccycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
142 workram:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
143 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
144 mov (%r9, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
145 jmp inccycles
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
146 vdp_psg:
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
147 test $0x2700E0, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
148 jnz crash
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
149 and $0x1F, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
150 jmp do_vdp_port_read
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
151 cart:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
152 mov (%r8, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
153 inccycles:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
154 add $4, %rax
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
155 cmp %rbp, %rax
59
32650c77008a ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Mike Pavone <pavone@retrodev.com>
parents: 57
diff changeset
156 jge do_limit
32650c77008a ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Mike Pavone <pavone@retrodev.com>
parents: 57
diff changeset
157 ret
32650c77008a ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Mike Pavone <pavone@retrodev.com>
parents: 57
diff changeset
158 do_limit:
32650c77008a ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Mike Pavone <pavone@retrodev.com>
parents: 57
diff changeset
159 push %rcx
32650c77008a ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Mike Pavone <pavone@retrodev.com>
parents: 57
diff changeset
160 call handle_cycle_limit
32650c77008a ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Mike Pavone <pavone@retrodev.com>
parents: 57
diff changeset
161 pop %rcx
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
162 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
163
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
164 .global m68k_read_long_scratch1
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parents: 17
diff changeset
165 m68k_read_long_scratch1:
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parents: 17
diff changeset
166 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
167 call m68k_read_word_scratch1
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Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
168 mov %cx, %di
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
169 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
170 add $2, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
171 call m68k_read_word_scratch1
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Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
172 and $0xFFFF, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
173 shl $16, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
174 or %edi, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
175 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
176
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
177 .global m68k_read_byte_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
178 m68k_read_byte_scratch1:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
179 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
180 /* deal with byte swapping */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
181 xor $1, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
182 cmp $0x400000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
183 jle cart_b
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
184 cmp $0xE00000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
185 jge workram_b
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
186 xor %cl, %cl
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
187 dec %cl
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
188 jmp inccycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
189 workram_b:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
190 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
191 mov (%r9, %rcx), %cl
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
192 jmp inccycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
193 cart_b:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
194 mov (%r8, %rcx), %cl
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
195 jmp inccycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
196
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
197 ret_addr_msg:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
198 .asciz "Program modified return address on stack: found %X, expected %X\n"
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parents: 17
diff changeset
199
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parents: 17
diff changeset
200 .global m68k_modified_ret_addr
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parents: 17
diff changeset
201 m68k_modified_ret_addr:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
202 lea ret_addr_msg(%rip), %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
203 mov %rcx, %rsi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
204 mov 8(%rsp), %rdx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
205 call printf
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
206 mov $1, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
207 call exit
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
208
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
209 dyn_addr_msg:
44e661913a51 Add preliminary support for JMP
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parents: 18
diff changeset
210 .asciz "Program needs dynamically calculated native address\n"
44e661913a51 Add preliminary support for JMP
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parents: 18
diff changeset
211
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
212 .global m68k_native_addr
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Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
213 m68k_native_addr:
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Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
214 lea dyn_addr_msg(%rip), %rdi
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
215 call puts
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
216 mov $1, %rdi
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
217 call exit
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
218
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
219 .global m68k_save_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
220 m68k_save_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
221 mov %bl, 1(%rsi) /* N Flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
222 mov %bh, 2(%rsi) /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
223 mov %dl, 3(%rsi) /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
224 mov %dh, 4(%rsi) /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
225 mov %r10d, 8(%rsi) /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
226 mov %r11d, 12(%rsi) /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
227 mov %r12d, 16(%rsi) /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
228 mov %r13d, 40(%rsi) /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
229 mov %r14d, 44(%rsi) /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
230 mov %r15d, 68(%rsi) /* a7 */
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
231 mov %eax, 76(%rsi) /* current cycle count */
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
232 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
233
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
234 .global m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents: 17
diff changeset
235 m68k_load_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
236 mov 1(%rsi), %bl /* N Flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
237 mov 2(%rsi), %bh /* V flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
238 mov 3(%rsi), %dl /* Z flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
239 mov 4(%rsi), %dh /* C flag */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
240 mov 8(%rsi), %r10d /* d0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
241 mov 12(%rsi), %r11d /* d1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
242 mov 16(%rsi), %r12d /* d2 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
243 mov 40(%rsi), %r13d /* a0 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
244 mov 44(%rsi), %r14d /* a1 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
245 mov 68(%rsi), %r15d /* a7 */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
246 mov 72(%rsi), %ebp /* target cycle count */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
247 mov 76(%rsi), %eax /* current cycle count */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
248 mov 80(%rsi), %r8d /* cartridge address */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
249 mov 88(%rsi), %r9d /* work ram address */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
250 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
251
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
252 .global m68k_start_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
253 m68k_start_context:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
254 call m68k_load_context
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
255 jmp *%rdi