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annotate lc8951.c @ 2058:70260f6051dd segacd

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Initial work on CDC emulation
author Michael Pavone <pavone@retrodev.com>
date Fri, 21 Jan 2022 20:24:48 -0800
parents
children 07ed42bd7b4c
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rev   line source
2058
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1 #include "lc8951.h"
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2
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3 enum {
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4 COMIN,
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5 IFSTAT,
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6 DBCL,
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7 DBCH,
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8 HEAD0,
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9 HEAD1,
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10 HEAD2,
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11 HEAD3,
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12 PTL,
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13 PTH,
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14 WAL,
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15 WAH,
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16 STAT0,
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17 STAT1,
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18 STAT2,
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19 STAT3,
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20
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21 SBOUT = COMIN,
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22 IFCTRL = IFSTAT,
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23 DACL = HEAD0,
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24 DACH = HEAD1,
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25 DTTRG = HEAD2,
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26 DTACK = HEAD3,
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27 WAL_WRITE = PTL,
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28 WAH_WRITE = PTH,
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29 CTRL0 = WAL,
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30 CTRL1 = WAH,
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31 PTL_WRITE = STAT0,
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32 PTH_WRITE = STAT1,
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33 RESET = STAT3
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34 };
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35
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36 //IFCTRL
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37 #define BIT_CMDIEN 0x80
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38 #define BIT_DTEIEN 0x40
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39 #define BIT_CECIEN 0x20
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40 #define BIT_CMDBK 0x10
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41 #define BIT_DTWAI 0x08
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42 #define BIT_STWAI 0x04
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43 #define BIT_DOUTEN 0x02
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44 #define BIT_SOUTEN 0x01
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45
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46 //IFSTAT
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47 #define BIT_CMDI 0x80
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48 #define BIT_DTEI 0x40
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49 #define BIT_DECI 0x20
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50 #define BIT_DTBSY 0x08
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51 #define BIT_STBSY 0x04
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52 #define BIT_DTEN 0x02
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53 #define BIT_STEN 0x01
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54
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55 //datasheet timing info
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56 //3 cycles for memory operation
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57 //6 cycles min for DMA-mode host transfer
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58
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59 void lc8951_init(lc8951 *context)
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60 {
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61 //This seems to vary somewhat between Sega CD models
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62 //unclear if the difference is in the lc8951 or gate array
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63 context->regs[IFSTAT] = 0xFF;
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64 context->ar_mask = 0x1F;
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65 }
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66
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67 void lc8951_reg_write(lc8951 *context, uint8_t value)
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68 {
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69 switch (context->ar)
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70 {
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71 case SBOUT:
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72 context->regs[context->ar] = value;
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73 if (context->ifctrl & BIT_SOUTEN) {
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74 context->regs[IFSTAT] &= ~BIT_STBSY;
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75 }
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76 break;
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77 case IFCTRL:
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78 context->ifctrl = value;
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79 if (!(value & BIT_SOUTEN)) {
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80 context->regs[IFSTAT] |= BIT_STBSY;
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81 }
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82 if (!(value & BIT_DOUTEN)) {
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83 context->regs[IFSTAT] |= BIT_DTBSY;
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84 }
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85 break;
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86 case DBCL:
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87 context->regs[context->ar] = value;
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88 break;
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89 case DBCH:
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90 context->regs[context->ar] = value & 0xF;
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91 break;
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92 case DACL:
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93 context->dac &= 0xFF00;
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94 context->dac |= value;
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95 break;
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96 case DACH:
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97 context->dac &= 0xFF;
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98 context->dac |= value << 8;
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99 break;
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100 case DTTRG:
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101 if (value & BIT_DOUTEN) {
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102 context->regs[IFSTAT] &= ~BIT_DTBSY;
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103 }
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104 break;
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105 case DTACK:
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106 context->regs[IFSTAT] |= BIT_DTEI;
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107 break;
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108 case WAL_WRITE:
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109 context->regs[WAL] = value;
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110 break;
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111 case WAH_WRITE:
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112 context->regs[WAH] = value;
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113 break;
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114 case PTL_WRITE:
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115 context->regs[PTL] = value;
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116 break;
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117 case PTH_WRITE:
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118 context->regs[PTH] = value;
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119 break;
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120 case RESET:
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121 context->comin_count = 0;
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122 context->regs[IFSTAT] = 0xFF;
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123 break;
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124 default:
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125 break;
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126 }
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127 if (context->ar != SBOUT) {
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128 context->ar++;
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129 context->ar &= context->ar_mask;
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130 }
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131 }
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132
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133 uint8_t lc8951_reg_read(lc8951 *context)
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134 {
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135 uint8_t value;
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136 if (context->ar == COMIN) {
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137 if (!context->comin_count) {
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138 return 0xFF;
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139 }
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140 value = context->comin[(context->comin_write - context->comin_count)&sizeof(context->comin)];
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141 context->comin_count--;
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142 if (!context->comin_count) {
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143 context->regs[IFSTAT] |= BIT_CMDI;
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144 }
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145 return value;
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146 }
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147 if (context->ar == STAT3) {
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148 context->regs[IFSTAT] |= BIT_DECI;
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149 }
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150 if (context->ar >= sizeof(context->regs)) {
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151 value = 0xFF;
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152 } else {
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153 value = context->regs[context->ar];
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154 }
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155 context->ar++;
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156 context->ar &= context->ar_mask;
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157 return value;
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158 }
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159
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160 void lc8951_ar_write(lc8951 *context, uint8_t value)
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161 {
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162 context->ar = value & context->ar_mask;
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163 }