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annotate jagcpu.h @ 1374:8f404b1fa572

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Go back to resetting the refresh counter after a DMA. Probably not quite correct as it is probably reset on VDP triggered refresh, but this is close enough for now given the general limitations with my refresh code. VDP FIFO Testing seems to be passing 100% reliably again (was occassionally failing still with the last commit)
author Michael Pavone <pavone@retrodev.com>
date Tue, 23 May 2017 23:47:40 -0700
parents c48d5191ddc9
children 10c7f1e44c47
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1 #ifndef JAGCPU_H_
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2 #define JAGCPU_H_
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3
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4 enum {
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5 JAG_ADD,
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6 JAG_ADDC,
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7 JAG_ADDQ,
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8 JAG_ADDQT,
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9 JAG_SUB,
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10 JAG_SUBC,
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11 JAG_SUBQ,
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12 JAG_SUBQT,
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13 JAG_NEG,
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14 JAG_AND,
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15 JAG_OR,
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16 JAG_XOR,
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17 JAG_NOT,
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18 JAG_BTST,
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19 JAG_BSET,
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20 JAG_BCLR,
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21 JAG_MULT,
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22 JAG_IMULT,
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23 JAG_IMULTN,
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24 JAG_RESMAC,
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25 JAG_IMACN,
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26 JAG_DIV,
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27 JAG_ABS,
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28 JAG_SH,
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29 JAG_SHLQ,
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30 JAG_SHRQ,
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31 JAG_SHA,
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32 JAG_SHARQ,
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33 JAG_ROR,
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34 JAG_RORQ,
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35 JAG_CMP,
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36 JAG_CMPQ,
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37 GPU_SAT8,
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38 DSP_SUBQMOD = GPU_SAT8,
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39 GPU_SAT16,
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40 DSP_SAT16S = GPU_SAT16,
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41 JAG_MOVE,
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42 JAG_MOVEQ,
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43 JAG_MOVETA,
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44 JAG_MOVEFA,
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45 JAG_MOVEI,
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46 JAG_LOADB,
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47 JAG_LOADW,
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48 JAG_LOAD,
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49 GPU_LOADP,
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50 DSP_SAT32S = GPU_LOADP,
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51 JAG_LOAD_R14_REL,
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52 JAG_LOAD_R15_REL,
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53 JAG_STOREB,
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54 JAG_STOREW,
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55 JAG_STORE,
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56 GPU_STOREP,
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57 DSP_MIRROR = GPU_STOREP,
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58 JAG_STORE_R14_REL,
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59 JAG_STORE_R15_REL,
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60 JAG_MOVE_PC,
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61 JAG_JUMP,
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62 JAG_JR,
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63 JAG_MMULT,
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64 JAG_MTOI,
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65 JAG_NORMI,
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66 JAG_NOP,
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67 JAG_LOAD_R14_INDEXED,
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68 JAG_LOAD_R15_INDEXED,
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69 JAG_STORE_R14_INDEXED,
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70 JAG_STORE_R15_INDEXED,
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71 GPU_SAT24,
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72 GPU_PACK,
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73 DSP_ADDQMOD = GPU_PACK,
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74 GPU_UNPACK //virtual opcode, UNPACK is PACK with a reg1 field set to 1
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75 };
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76
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77 #define JAGCPU_NOREG -1
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78
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79
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80 typedef struct {
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81 cpu_options gen;
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82 int8_t regs[32];
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83 int8_t result;
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84 int8_t resultreg;
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85 int8_t bankptr;
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86 uint8_t is_gpu;
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87 } jag_cpu_options;
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88
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89 typedef struct {
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90 uint32_t read_high;
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91 } jag_gpu;
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92
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93 typedef struct {
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94 uint8_t mac_high;
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95 uint8_t modulo;
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96 } jag_dsp;
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97
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98 typedef struct {
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99 uint32_t cycles;
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100 uint32_t regs[64];
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101 uint32_t *main;
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102 uint32_t *alt;
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103 uint32_t pc;
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104 uint32_t result;
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105 uint32_t flags;
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106 uint32_t flags_pending;
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107 uint32_t remainder;
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108 union {
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109 jag_gpu gpu;
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110 jag_dsp dsp;
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111 };
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112 int8_t writeback;
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113 int8_t resultreg;
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114 uint8_t is_gpu;
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115 } jag_cpu;
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116
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117 uint16_t jag_opcode(uint16_t inst, uint8_t is_gpu);
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118 char * jag_cc(uint16_t inst);
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119 uint16_t jag_reg2(uint16_t inst);
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120 uint32_t jag_jr_dest(uint16_t inst, uint32_t address);
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121 int jag_cpu_disasm(uint16_t **stream, uint32_t address, char *dst, uint8_t is_gpu, uint8_t labels);
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122
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123 #endif