Mercurial > repos > blastem

annotate test_int_timing.c @ 1374:8f404b1fa572

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Go back to resetting the refresh counter after a DMA. Probably not quite correct as it is probably reset on VDP triggered refresh, but this is close enough for now given the general limitations with my refresh code. VDP FIFO Testing seems to be passing 100% reliably again (was occassionally failing still with the last commit)
author Michael Pavone <pavone@retrodev.com>
date Tue, 23 May 2017 23:47:40 -0700
parents aa6e0914dcd7
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1172
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 /*
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2 Copyright 2017 Michael Pavone
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
3 This file is part of BlastEm.
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
5 */
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #include <stdio.h>
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
7 #include "vdp.h"
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
8
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
9 int headless = 1;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
10
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
11 uint32_t render_map_color(uint8_t r, uint8_t g, uint8_t b)
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
12 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
13 return 0;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
14 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
15
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
16 uint16_t read_dma_value(uint32_t address)
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
17 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
18 return 0;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
19 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
20
1176
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
21 uint32_t *render_get_framebuffer(uint8_t which, int *pitch)
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
22 {
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
23 *pitch = 0;
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
24 return NULL;
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
25 }
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
26
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
27 void render_framebuffer_updated(uint8_t which, int width)
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
28 {
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
29 }
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
30
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
31 void warning(char *format, ...)
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
32 {
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
33 }
aa6e0914dcd7 Add some dummy functions to test_int_timing so debug builds of it succeed
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
34
1172
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
35
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
36 int main(int argc, char **argv)
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
37 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
38 vdp_context context;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
39 int ret = 0;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
40 init_vdp_context(&context, 0);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
41 vdp_control_port_write(&context, 0x8000 | BIT_PAL_SEL);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
42 vdp_control_port_write(&context, 0x8100 | BIT_DISP_EN | BIT_VINT_EN | BIT_MODE_5);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
43 puts("Testing H32 Mode");
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
44 while (!(context.flags2 & FLAG2_VINT_PENDING))
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
45 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
46 vdp_run_context(&context, context.cycles + 1);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
47 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
48 vdp_int_ack(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
49 uint32_t vint_cycle = vdp_next_vint(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
50 while (!(context.flags2 & FLAG2_VINT_PENDING))
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
51 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
52 vdp_run_context(&context, context.cycles + 1);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
53 uint32_t vint_cycle2 = vdp_next_vint(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
54 if (vint_cycle2 != vint_cycle) {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
55 printf("VINT Cycle changed from %d to %d @ line %d, slot %d\n", vint_cycle, vint_cycle2, context.vcounter, context.hslot);;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
56 ret = 1;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
57 vint_cycle = vint_cycle2;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
58 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
59 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
60 vdp_int_ack(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
61 puts("Testing H40 Mode");
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
62 vdp_control_port_write(&context, 0x8C81);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
63 while (!(context.flags2 & FLAG2_VINT_PENDING))
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
64 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
65 vdp_run_context(&context, context.cycles + 1);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
66 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
67 vdp_int_ack(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
68 vint_cycle = vdp_next_vint(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
69 while (!(context.flags2 & FLAG2_VINT_PENDING))
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
70 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
71 vdp_run_context(&context, context.cycles + 1);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
72 uint32_t vint_cycle2 = vdp_next_vint(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
73 if (vint_cycle2 != vint_cycle) {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
74 printf("VINT Cycle changed from %d to %d @ line %d, slot %d\n", vint_cycle, vint_cycle2, context.vcounter, context.hslot);;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
75 ret = 1;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
76 vint_cycle = vint_cycle2;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
77 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
78 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
79 vdp_int_ack(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
80 puts("Testing Mode 4");
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
81 vdp_control_port_write(&context, 0x8C00);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
82 vdp_control_port_write(&context, 0x8100 | BIT_DISP_EN | BIT_VINT_EN);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
83 while (!(context.flags2 & FLAG2_VINT_PENDING))
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
84 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
85 vdp_run_context(&context, context.cycles + 1);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
86 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
87 context.flags2 &= ~FLAG2_VINT_PENDING;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
88 vint_cycle = vdp_next_vint(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
89 while (!(context.flags2 & FLAG2_VINT_PENDING))
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
90 {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
91 vdp_run_context(&context, context.cycles + 1);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
92 uint32_t vint_cycle2 = vdp_next_vint(&context);
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
93 if (vint_cycle2 != vint_cycle) {
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
94 printf("VINT Cycle changed from %d to %d @ line %d, slot %d\n", vint_cycle, vint_cycle2, context.vcounter, context.hslot);;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
95 ret = 1;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
96 vint_cycle = vint_cycle2;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
97 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
98 }
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
99 printf("Result: %s\n", ret ? "failure" : "success");
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
100 return ret;
14eb8ff4fb03 Added synthetic test for tracking down interrupt timing issues
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
101 }