Mercurial > repos > blastem
annotate gen_arm.c @ 950:938c72a2f7a9
Initial work on pause menu
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 11 Apr 2016 20:56:48 -0700 |
parents | 724bbec47f86 |
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1 /* |
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2 Copyright 2014 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_arm.h" |
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7 #include "mem.h" |
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8 #include <stdio.h> |
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9 #include <stdlib.h> |
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10 |
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11 #define OP_FIELD_SHIFT 21u |
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12 |
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13 //Data processing format instructions |
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14 #define OP_AND 0x0u |
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15 #define OP_EOR (0x1u << OP_FIELD_SHIFT) |
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16 #define OP_SUB (0x2u << OP_FIELD_SHIFT) |
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17 #define OP_RSB (0x3u << OP_FIELD_SHIFT) |
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18 #define OP_ADD (0x4u << OP_FIELD_SHIFT) |
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19 #define OP_ADC (0x5u << OP_FIELD_SHIFT) |
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20 #define OP_SBC (0x6u << OP_FIELD_SHIFT) |
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21 #define OP_RSC (0x7u << OP_FIELD_SHIFT) |
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22 #define OP_TST (0x8u << OP_FIELD_SHIFT) |
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23 #define OP_TEQ (0x9u << OP_FIELD_SHIFT) |
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24 #define OP_CMP (0xAu << OP_FIELD_SHIFT) |
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25 #define OP_CMN (0xBu << OP_FIELD_SHIFT) |
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26 #define OP_ORR (0xCu << OP_FIELD_SHIFT) |
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27 #define OP_MOV (0xDu << OP_FIELD_SHIFT) |
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28 #define OP_BIC (0xEu << OP_FIELD_SHIFT) |
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29 #define OP_MVN (0xFu << OP_FIELD_SHIFT) |
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30 |
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31 //branch instructions |
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32 #define OP_B 0xA000000u |
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33 #define OP_BL 0xB000000u |
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34 #define OP_BX 0x12FFF10u |
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35 |
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36 //load/store |
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37 #define OP_STR 0x4000000u |
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38 #define OP_LDR 0x4100000u |
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39 #define OP_STM 0x8000000u |
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40 #define OP_LDM 0x8100000u |
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41 #define POST_IND 0u |
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42 #define PRE_IND 0x1000000u |
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43 #define DIR_DOWN 0u |
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44 #define DIR_UP 0x0800000u |
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45 #define SZ_W 0u |
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46 #define SZ_B 0x0400000u |
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47 #define WRITE_B 0x0200000u |
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48 #define OFF_IMM 0u |
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49 #define OFF_REG 0x2000000u |
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50 |
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51 #define PUSH (OP_STR | PRE_IND | OFF_IMM | SZ_W | WRITE_B | DIR_DOWN | sizeof(uint32_t) | (sp << 16)) |
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52 #define POP (OP_LDR | POST_IND | OFF_IMM | SZ_W | DIR_UP | sizeof(uint32_t) | (sp << 16)) |
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53 #define PUSHM (OP_STM | PRE_IND | SZ_W | WRITE_B | DIR_DOWN | (sp << 16)) |
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54 #define POPM (OP_LDM | POST_IND | SZ_W | WRITE_B | DIR_UP | (sp << 16)) |
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55 |
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56 #define IMMED 0x2000000u |
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57 #define REG 0u |
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58 |
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59 |
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60 uint32_t make_immed(uint32_t val) |
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61 { |
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62 uint32_t rot_amount = 0; |
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63 for (; rot_amount < 0x20; rot_amount += 2) |
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64 { |
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65 uint32_t test_mask = ~(0xFF << rot_amount | 0xFF >> (32-rot_amount)); |
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66 if (!(test_mask & val)) { |
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67 return val << rot_amount | val >> (32-rot_amount) | rot_amount << 7; |
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68 } |
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69 } |
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70 return INVALID_IMMED; |
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71 } |
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72 |
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73 void check_alloc_code(code_info *code) |
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74 { |
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75 if (code->cur == code->last) { |
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76 size_t size = CODE_ALLOC_SIZE; |
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77 uint32_t *next_code = alloc_code(&size); |
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78 if (!next_code) { |
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79 fatal_error("Failed to allocate memory for generated code\n"); |
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80 } |
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81 if (next_code = code->last + RESERVE_WORDS) { |
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82 //new chunk is contiguous with the current one |
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83 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS; |
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84 } else { |
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85 uint32_t * from = code->cur + 2; |
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86 if (next_code - from < 0x400000 || from - next_code <= 0x400000) { |
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87 *from = CC_AL | OP_B | ((next_code - from) & 0xFFFFFF); |
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88 } else { |
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89 //push r0 onto the stack |
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90 *(from++) = CC_AL | PUSH; |
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91 uint32_t immed = make_immed((uint32_t)next_code); |
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92 if (immed == INVALID_IMMED) { |
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93 //Load target into r0 from word after next instruction into register 0 |
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94 *(from++) = CC_AL | OP_LDR | OFF_IMM | DIR_DOWN | PRE_IND | SZ_W | (pc << 16) | 4; |
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95 from[1] = (uint32_t)next_code; |
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96 } else { |
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97 //Load target into r0 |
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98 *(from++) = CC_AL | OP_MOV | IMMED | NO_COND | immed; |
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99 } |
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100 //branch to address in r0 |
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101 *from = CC_AL | OP_BX; |
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102 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS; |
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103 //pop r0 |
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104 *(next_code++) = CC_AL | POP; |
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105 code->cur = next_code; |
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106 } |
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107 } |
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108 } |
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109 } |
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110 |
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111 uint32_t data_proc(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t src2) |
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112 { |
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113 check_alloc_code(code); |
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114 *(code->cur++) = cond | op | set_cond | (src1 << 16) | (dst << 12) | src2; |
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115 |
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116 return CODE_OK; |
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117 } |
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118 |
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119 uint32_t data_proci(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t immed) |
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120 { |
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121 immed = make_immed(immed); |
554
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122 if (immed == INVALID_IMMED) { |
553
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123 return immed; |
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124 } |
554
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125 return data_proc(code, cond, op | IMMED, set_cond, dst, src1, immed); |
553
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126 } |
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127 |
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128 //TODO: support shifted register for op2 |
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129 |
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130 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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131 { |
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132 return data_proc(code, CC_AL, OP_AND, set_cond, dst, src1, src2); |
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133 } |
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134 |
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135 uint32_t andi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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136 { |
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137 return data_proci(code, CC_AL, OP_AND, set_cond, dst, src1, immed); |
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138 } |
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139 |
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140 uint32_t and_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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141 { |
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142 return data_proc(code, cc, OP_AND, set_cond, dst, src1, src2); |
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143 } |
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144 |
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145 uint32_t andi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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146 { |
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147 return data_proci(code, cc, OP_AND, set_cond, dst, src1, immed); |
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148 } |
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149 |
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150 uint32_t eor(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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151 { |
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152 return data_proc(code, CC_AL, OP_EOR, set_cond, dst, src1, src2); |
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153 } |
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154 |
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155 uint32_t eori(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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156 { |
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157 return data_proci(code, CC_AL, OP_EOR, set_cond, dst, src1, immed); |
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158 } |
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159 |
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160 uint32_t eor_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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161 { |
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162 return data_proc(code, cc, OP_EOR, set_cond, dst, src1, src2); |
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163 } |
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164 |
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165 uint32_t eori_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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166 { |
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167 return data_proci(code, cc, OP_EOR, set_cond, dst, src1, immed); |
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168 } |
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169 |
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170 uint32_t sub(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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171 { |
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172 return data_proc(code, CC_AL, OP_SUB, set_cond, dst, src1, src2); |
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173 } |
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174 |
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175 uint32_t subi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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176 { |
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177 return data_proci(code, CC_AL, OP_SUB, set_cond, dst, src1, immed); |
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178 } |
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179 |
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180 uint32_t sub_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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181 { |
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182 return data_proc(code, cc, OP_SUB, set_cond, dst, src1, src2); |
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|
183 } |
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184 |
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185 uint32_t subi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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|
186 { |
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187 return data_proci(code, cc, OP_SUB, set_cond, dst, src1, immed); |
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|
188 } |
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189 |
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190 uint32_t rsb(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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|
191 { |
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|
192 return data_proc(code, CC_AL, OP_RSB, set_cond, dst, src1, src2); |
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|
193 } |
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|
194 |
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|
195 uint32_t rsbi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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|
196 { |
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197 return data_proci(code, CC_AL, OP_RSB, set_cond, dst, src1, immed); |
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|
198 } |
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199 |
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200 uint32_t rsb_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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|
201 { |
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|
202 return data_proc(code, cc, OP_RSB, set_cond, dst, src1, src2); |
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|
203 } |
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|
204 |
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|
205 uint32_t rsbi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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diff
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|
206 { |
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|
207 return data_proci(code, cc, OP_RSB, set_cond, dst, src1, immed); |
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|
208 } |
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|
209 |
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diff
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|
210 uint32_t add(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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|
211 { |
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|
212 return data_proc(code, CC_AL, OP_ADD, set_cond, dst, src1, src2); |
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|
213 } |
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diff
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|
214 |
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diff
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|
215 uint32_t addi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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|
216 { |
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|
217 return data_proci(code, CC_AL, OP_ADD, set_cond, dst, src1, immed); |
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|
218 } |
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diff
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|
219 |
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|
220 uint32_t add_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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|
221 { |
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|
222 return data_proc(code, cc, OP_ADD, set_cond, dst, src1, src2); |
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|
223 } |
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diff
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|
224 |
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|
225 uint32_t addi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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diff
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|
226 { |
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|
227 return data_proci(code, cc, OP_ADD, set_cond, dst, src1, immed); |
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|
228 } |
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diff
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|
229 |
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|
230 uint32_t adc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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|
231 { |
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|
232 return data_proc(code, CC_AL, OP_ADC, set_cond, dst, src1, src2); |
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|
233 } |
1af6c1052993
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diff
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|
234 |
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diff
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|
235 uint32_t adci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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diff
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|
236 { |
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|
237 return data_proci(code, CC_AL, OP_ADC, set_cond, dst, src1, immed); |
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|
238 } |
1af6c1052993
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parents:
diff
changeset
|
239 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
240 uint32_t adc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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241 { |
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242 return data_proc(code, cc, OP_ADC, set_cond, dst, src1, src2); |
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243 } |
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244 |
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245 uint32_t adci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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246 { |
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247 return data_proci(code, cc, OP_ADC, set_cond, dst, src1, immed); |
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248 } |
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249 |
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250 uint32_t sbc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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251 { |
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252 return data_proc(code, CC_AL, OP_SBC, set_cond, dst, src1, src2); |
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253 } |
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254 |
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255 uint32_t sbci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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256 { |
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257 return data_proci(code, CC_AL, OP_SBC, set_cond, dst, src1, immed); |
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258 } |
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259 |
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260 uint32_t sbc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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261 { |
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262 return data_proc(code, cc, OP_SBC, set_cond, dst, src1, src2); |
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263 } |
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264 |
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265 uint32_t sbci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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266 { |
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267 return data_proci(code, cc, OP_SBC, set_cond, dst, src1, immed); |
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268 } |
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269 |
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270 uint32_t rsc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
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271 { |
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272 return data_proc(code, CC_AL, OP_RSC, set_cond, dst, src1, src2); |
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273 } |
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274 |
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275 uint32_t rsci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
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276 { |
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277 return data_proci(code, CC_AL, OP_RSC, set_cond, dst, src1, immed); |
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278 } |
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279 |
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280 uint32_t rsc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
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281 { |
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282 return data_proc(code, cc, OP_RSC, set_cond, dst, src1, src2); |
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283 } |
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284 |
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285 uint32_t rsci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
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286 { |
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287 return data_proci(code, cc, OP_RSC, set_cond, dst, src1, immed); |
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288 } |
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289 |
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290 uint32_t tst(code_info *code, uint32_t src1, uint32_t src2) |
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291 { |
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292 return data_proc(code, CC_AL, OP_TST, SET_COND, r0, src1, src2); |
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|
293 } |
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294 |
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295 uint32_t tsti(code_info *code, uint32_t src1, uint32_t immed) |
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|
296 { |
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297 return data_proci(code, CC_AL, OP_TST, SET_COND, r0, src1, immed); |
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|
298 } |
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|
299 |
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|
300 uint32_t tst_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
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changeset
|
301 { |
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|
302 return data_proc(code, cc, OP_TST, SET_COND, r0, src1, src2); |
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|
303 } |
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diff
changeset
|
304 |
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changeset
|
305 uint32_t tsti_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
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diff
changeset
|
306 { |
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diff
changeset
|
307 return data_proci(code, cc, OP_TST, SET_COND, r0, src1, immed); |
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diff
changeset
|
308 } |
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diff
changeset
|
309 |
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diff
changeset
|
310 uint32_t teq(code_info *code, uint32_t src1, uint32_t src2) |
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diff
changeset
|
311 { |
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|
312 return data_proc(code, CC_AL, OP_TEQ, SET_COND, r0, src1, src2); |
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changeset
|
313 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
314 |
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changeset
|
315 uint32_t teqi(code_info *code, uint32_t src1, uint32_t immed) |
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diff
changeset
|
316 { |
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diff
changeset
|
317 return data_proci(code, CC_AL, OP_TEQ, SET_COND, r0, src1, immed); |
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diff
changeset
|
318 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
319 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
320 uint32_t teq_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
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parents:
diff
changeset
|
321 { |
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diff
changeset
|
322 return data_proc(code, cc, OP_TEQ, SET_COND, r0, src1, src2); |
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parents:
diff
changeset
|
323 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
324 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
325 uint32_t teqi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
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parents:
diff
changeset
|
326 { |
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diff
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|
327 return data_proci(code, cc, OP_TEQ, SET_COND, r0, src1, immed); |
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parents:
diff
changeset
|
328 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
329 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
330 uint32_t cmp(code_info *code, uint32_t src1, uint32_t src2) |
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diff
changeset
|
331 { |
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parents:
diff
changeset
|
332 return data_proc(code, CC_AL, OP_CMP, SET_COND, r0, src1, src2); |
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parents:
diff
changeset
|
333 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
334 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
335 uint32_t cmpi(code_info *code, uint32_t src1, uint32_t immed) |
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parents:
diff
changeset
|
336 { |
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diff
changeset
|
337 return data_proci(code, CC_AL, OP_CMP, SET_COND, r0, src1, immed); |
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parents:
diff
changeset
|
338 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
339 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
340 uint32_t cmp_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
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parents:
diff
changeset
|
341 { |
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diff
changeset
|
342 return data_proc(code, cc, OP_CMP, SET_COND, r0, src1, src2); |
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
343 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
344 |
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
345 uint32_t cmpi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
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parents:
diff
changeset
|
346 { |
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diff
changeset
|
347 return data_proci(code, cc, OP_CMP, SET_COND, r0, src1, immed); |
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parents:
diff
changeset
|
348 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
349 |
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diff
changeset
|
350 uint32_t cmn(code_info *code, uint32_t src1, uint32_t src2) |
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parents:
diff
changeset
|
351 { |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 return data_proc(code, CC_AL, OP_CMN, SET_COND, r0, src1, src2); |
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parents:
diff
changeset
|
353 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 |
1af6c1052993
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parents:
diff
changeset
|
355 uint32_t cmni(code_info *code, uint32_t src1, uint32_t immed) |
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parents:
diff
changeset
|
356 { |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
357 return data_proci(code, CC_AL, OP_CMN, SET_COND, r0, src1, immed); |
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 } |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
359 |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 uint32_t cmn_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc) |
1af6c1052993
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
362 return data_proc(code, cc, OP_CMN, SET_COND, r0, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
363 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 uint32_t cmni_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
367 return data_proci(code, cc, OP_CMN, SET_COND, r0, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 uint32_t orr(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 return data_proc(code, CC_AL, OP_ORR, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 uint32_t orri(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
377 return data_proci(code, CC_AL, OP_ORR, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 uint32_t orr_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 return data_proc(code, cc, OP_ORR, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
385 uint32_t orri_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 return data_proci(code, cc, OP_ORR, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 uint32_t mov(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 return data_proc(code, CC_AL, OP_MOV, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
393 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
395 uint32_t movi(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
396 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
397 return data_proci(code, CC_AL, OP_MOV, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
398 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 uint32_t mov_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
401 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 return data_proc(code, cc, OP_MOV, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
403 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
404 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
405 uint32_t movi_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
406 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 return data_proci(code, cc, OP_MOV, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 uint32_t bic(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 return data_proc(code, CC_AL, OP_BIC, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 uint32_t bici(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 return data_proci(code, CC_AL, OP_BIC, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 uint32_t bic_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 return data_proc(code, cc, OP_BIC, set_cond, dst, src1, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 uint32_t bici_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
426 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
427 return data_proci(code, cc, OP_BIC, set_cond, dst, src1, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
428 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 uint32_t mvn(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 return data_proc(code, CC_AL, OP_MVN, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 uint32_t mvni(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 return data_proci(code, CC_AL, OP_MVN, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 uint32_t mvn_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 return data_proc(code, cc, OP_MVN, set_cond, dst, 0, src2); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
444 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 uint32_t mvni_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 return data_proci(code, cc, OP_MVN, set_cond, dst, 0, immed); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 uint32_t branchi(code_info *code, uint32_t cc, uint32_t op, uint32_t *dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 uint32_t * from = code->cur + 2; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 if (dst - from >= 0x400000 && from - dst > 0x400000) { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 return INVALID_IMMED; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 *(code->cur++) = cc | op | ((dst - from) & 0xFFFFFF); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 uint32_t b(code_info *code, uint32_t *dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 return branchi(code, CC_AL, OP_B, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 uint32_t b_cc(code_info *code, uint32_t *dst, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 return branchi(code, cc, OP_B, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 uint32_t bl(code_info *code, uint32_t *dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 return branchi(code, CC_AL, OP_BL, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 uint32_t bl_cc(code_info *code, uint32_t *dst, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 return branchi(code, cc, OP_BL, dst); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 uint32_t bx(code_info *code, uint32_t dst) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 *(code->cur++) = CC_AL | OP_BX | dst; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
487 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 uint32_t bx_cc(code_info *code, uint32_t dst, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 *(code->cur++) = cc | OP_BX | dst; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 uint32_t push(code_info *code, uint32_t reg) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 *(code->cur++) = CC_AL | PUSH | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 uint32_t push_cc(code_info *code, uint32_t reg, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 *(code->cur++) = cc | PUSH | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 uint32_t pushm(code_info *code, uint32_t reglist) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
510 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
511 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
512 *(code->cur++) = CC_AL | PUSHM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
513 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
514 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
515 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
516 uint32_t pushm_cc(code_info *code, uint32_t reglist, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
519 *(code->cur++) = cc | PUSHM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
520 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
521 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 uint32_t pop(code_info *code, uint32_t reg) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 *(code->cur++) = CC_AL | POP | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
528 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
530 uint32_t pop_cc(code_info *code, uint32_t reg, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 *(code->cur++) = cc | POP | reg << 12; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 uint32_t popm(code_info *code, uint32_t reglist) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 *(code->cur++) = CC_AL | POPM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 } |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 uint32_t popm_cc(code_info *code, uint32_t reglist, uint32_t cc) |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 { |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 check_alloc_code(code); |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 *(code->cur++) = cc | POPM | reglist; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 return CODE_OK; |
1af6c1052993
Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 } |
684
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
550 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
551 uint32_t load_store_immoff(code_info *code, uint32_t op, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
552 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
553 if (offset >= 0x1000 || offset <= -0x1000) { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
554 return INVALID_IMMED; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
555 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
556 check_alloc_code(code); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
557 uint32_t instruction = cc | op | POST_IND | OFF_IMM | SZ_W | base << 16 | dst << 12; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
558 if (offset >= 0) { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
559 instruction |= offset | DIR_UP; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
560 } else { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
561 instruction |= (-offset) | DIR_DOWN; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
562 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
563 *(code->cur++) = instruction; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
564 return CODE_OK; |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
565 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
566 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
567 uint32_t ldr_cc(code_info *code, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
568 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
569 return load_store_immoff(code, OP_LDR, dst, base, offset, cc); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
570 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
571 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
572 uint32_t ldr(code_info *code, uint32_t dst, uint32_t base, int32_t offset) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
573 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
574 return ldr_cc(code, dst, base, offset, CC_AL); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
575 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
576 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
577 uint32_t str_cc(code_info *code, uint32_t src, uint32_t base, int32_t offset, uint32_t cc) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
578 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
579 return load_store_immoff(code, OP_STR, src, base, offset, cc); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
580 } |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
581 |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
582 uint32_t str(code_info *code, uint32_t src, uint32_t base, int32_t offset) |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
583 { |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
584 return str_cc(code, src, base, offset, CC_AL); |
bff307e03a94
Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents:
563
diff
changeset
|
585 } |