repos/blastem: gen_arm.c annotate

annotate gen_arm.c @ 563:c8fefa140c80

Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 24 Feb 2014 09:55:24 -0800
parents	474270dbff15
children	bff307e03a94

rev	line source
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 /*
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 Copyright 2014 Michael Pavone
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 This file is part of BlastEm.
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 */
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "gen_arm.h"
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "mem.h"
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include <stdio.h>
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <stdlib.h>
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	10
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define OP_FIELD_SHIFT 21u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	12
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 //Data processing format instructions
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define OP_AND 0x0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define OP_EOR (0x1u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define OP_SUB (0x2u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define OP_RSB (0x3u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define OP_ADD (0x4u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define OP_ADC (0x5u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define OP_SBC (0x6u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 #define OP_RSC (0x7u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 #define OP_TST (0x8u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 #define OP_TEQ (0x9u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 #define OP_CMP (0xAu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 #define OP_CMN (0xBu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 #define OP_ORR (0xCu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 #define OP_MOV (0xDu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 #define OP_BIC (0xEu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 #define OP_MVN (0xFu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	30
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 //branch instructions
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 #define OP_B 0xA000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 #define OP_BL 0xB000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 #define OP_BX 0x12FFF10u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	35
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 //load/store
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 #define OP_STR 0x4000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 #define OP_LDR 0x4100000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 #define OP_STM 0x8000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 #define OP_LDM 0x8100000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 #define POST_IND 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 #define PRE_IND 0x1000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 #define DIR_DOWN 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 #define DIR_UP 0x0800000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 #define SZ_W 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 #define SZ_B 0x0400000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 #define WRITE_B 0x0200000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 #define OFF_IMM 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 #define OFF_REG 0x2000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	50
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 #define PUSH (OP_STR \| PRE_IND \| OFF_IMM \| SZ_W \| WRITE_B \| DIR_DOWN \| sizeof(uint32_t) \| (sp << 16))
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 #define POP (OP_LDR \| POST_IND \| OFF_IMM \| SZ_W \| DIR_UP \| sizeof(uint32_t) \| (sp << 16))
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 #define PUSHM (OP_STM \| PRE_IND \| SZ_W \| WRITE_B \| DIR_DOWN \| (sp << 16))
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	54 #define POPM (OP_LDM \| POST_IND \| SZ_W \| WRITE_B \| DIR_UP \| (sp << 16))
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	55
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 #define IMMED 0x2000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 #define REG 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	58
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	59
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 uint32_t make_immed(uint32_t val)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 uint32_t rot_amount = 0;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 for (; rot_amount < 0x20; rot_amount += 2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 uint32_t test_mask = ~(0xFF << rot_amount \| 0xFF >> (32-rot_amount));
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 if (!(test_mask & val)) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 return val << rot_amount \| val >> (32-rot_amount) \| rot_amount << 7;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 return INVALID_IMMED;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	72
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 void check_alloc_code(code_info *code)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 {
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	75 if (code->cur == code->last) {
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 size_t size = CODE_ALLOC_SIZE;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 uint32_t *next_code = alloc_code(&size);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 if (!next_code) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 fputs("Failed to allocate memory for generated code\n", stderr);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 exit(1);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 }
563 c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic Michael Pavone <pavone@retrodev.com> parents: 554 diff changeset	82 if (next_code = code->last + RESERVE_WORDS) {
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 //new chunk is contiguous with the current one
563 c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic Michael Pavone <pavone@retrodev.com> parents: 554 diff changeset	84 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS;
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 } else {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 uint32_t * from = code->cur + 2;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 if (next_code - from < 0x400000 \|\| from - next_code <= 0x400000) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 *from = CC_AL \| OP_B \| ((next_code - from) & 0xFFFFFF);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 } else {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 //push r0 onto the stack
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 *(from++) = CC_AL \| PUSH;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 uint32_t immed = make_immed((uint32_t)next_code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 if (immed == INVALID_IMMED) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 //Load target into r0 from word after next instruction into register 0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 *(from++) = CC_AL \| OP_LDR \| OFF_IMM \| DIR_DOWN \| PRE_IND \| SZ_W \| (pc << 16) \| 4;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 from[1] = (uint32_t)next_code;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 } else {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 //Load target into r0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 *(from++) = CC_AL \| OP_MOV \| IMMED \| NO_COND \| immed;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 //branch to address in r0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 *from = CC_AL \| OP_BX;
563 c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic Michael Pavone <pavone@retrodev.com> parents: 554 diff changeset	103 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS;
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 //pop r0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 *(next_code++) = CC_AL \| POP;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 code->cur = next_code;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	111
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 uint32_t data_proc(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 check_alloc_code(code);
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	115 *(code->cur++) = cond \| op \| set_cond \| (src1 << 16) \| (dst << 12) \| src2;
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	116
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	119
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	120 uint32_t data_proci(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 immed = make_immed(immed);
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	123 if (immed == INVALID_IMMED) {
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 return immed;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 }
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	126 return data_proc(code, cond, op \| IMMED, set_cond, dst, src1, immed);
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	128
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	129 //TODO: support shifted register for op2
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	130
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 return data_proc(code, CC_AL, OP_AND, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	134 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	135
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 uint32_t andi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 return data_proci(code, CC_AL, OP_AND, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	140
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 uint32_t and_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 return data_proc(code, cc, OP_AND, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	145
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 uint32_t andi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 return data_proci(code, cc, OP_AND, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	150
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 uint32_t eor(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 return data_proc(code, CC_AL, OP_EOR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	154 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	155
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 uint32_t eori(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 return data_proci(code, CC_AL, OP_EOR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	160
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 uint32_t eor_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 return data_proc(code, cc, OP_EOR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	165
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 uint32_t eori_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 return data_proci(code, cc, OP_EOR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	170
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 uint32_t sub(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 return data_proc(code, CC_AL, OP_SUB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	175
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 uint32_t subi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 return data_proci(code, CC_AL, OP_SUB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	180
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 uint32_t sub_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 return data_proc(code, cc, OP_SUB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	185
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 uint32_t subi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 return data_proci(code, cc, OP_SUB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	190
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 uint32_t rsb(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 return data_proc(code, CC_AL, OP_RSB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	195
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 uint32_t rsbi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 return data_proci(code, CC_AL, OP_RSB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	200
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 uint32_t rsb_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 return data_proc(code, cc, OP_RSB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	205
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 uint32_t rsbi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 return data_proci(code, cc, OP_RSB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	210
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 uint32_t add(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 return data_proc(code, CC_AL, OP_ADD, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	215
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 uint32_t addi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 return data_proci(code, CC_AL, OP_ADD, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	220
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 uint32_t add_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 return data_proc(code, cc, OP_ADD, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	225
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 uint32_t addi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 return data_proci(code, cc, OP_ADD, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	230
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 uint32_t adc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 return data_proc(code, CC_AL, OP_ADC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	235
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 uint32_t adci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 return data_proci(code, CC_AL, OP_ADC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	240
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 uint32_t adc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 return data_proc(code, cc, OP_ADC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	245
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 uint32_t adci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 return data_proci(code, cc, OP_ADC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	250
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 uint32_t sbc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	252 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 return data_proc(code, CC_AL, OP_SBC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	255
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 uint32_t sbci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 return data_proci(code, CC_AL, OP_SBC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	260
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 uint32_t sbc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 return data_proc(code, cc, OP_SBC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	265
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 uint32_t sbci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 return data_proci(code, cc, OP_SBC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	270
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 uint32_t rsc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 return data_proc(code, CC_AL, OP_RSC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	274 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	275
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 uint32_t rsci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 return data_proci(code, CC_AL, OP_RSC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	279 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	280
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 uint32_t rsc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 return data_proc(code, cc, OP_RSC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	285
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 uint32_t rsci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 return data_proci(code, cc, OP_RSC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	290
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 uint32_t tst(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 return data_proc(code, CC_AL, OP_TST, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	294 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	295
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 uint32_t tsti(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 return data_proci(code, CC_AL, OP_TST, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	300
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 uint32_t tst_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 return data_proc(code, cc, OP_TST, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	305
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 uint32_t tsti_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 return data_proci(code, cc, OP_TST, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	309 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	310
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 uint32_t teq(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	313 return data_proc(code, CC_AL, OP_TEQ, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	314 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	315
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 uint32_t teqi(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	318 return data_proci(code, CC_AL, OP_TEQ, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	319 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	320
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	321 uint32_t teq_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	322 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 return data_proc(code, cc, OP_TEQ, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	324 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	325
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	326 uint32_t teqi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	328 return data_proci(code, cc, OP_TEQ, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	329 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	330
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 uint32_t cmp(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	333 return data_proc(code, CC_AL, OP_CMP, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	334 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	335
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	336 uint32_t cmpi(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 return data_proci(code, CC_AL, OP_CMP, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	340
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 uint32_t cmp_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	343 return data_proc(code, cc, OP_CMP, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	345
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 uint32_t cmpi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	347 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	348 return data_proci(code, cc, OP_CMP, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	349 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	350
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	351 uint32_t cmn(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 return data_proc(code, CC_AL, OP_CMN, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	354 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	355
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 uint32_t cmni(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	358 return data_proci(code, CC_AL, OP_CMN, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	360
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 uint32_t cmn_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 return data_proc(code, cc, OP_CMN, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	364 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	365
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 uint32_t cmni_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 return data_proci(code, cc, OP_CMN, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	369 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	370
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 uint32_t orr(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 return data_proc(code, CC_AL, OP_ORR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	375
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 uint32_t orri(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 return data_proci(code, CC_AL, OP_ORR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	379 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	380
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	381 uint32_t orr_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	382 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 return data_proc(code, cc, OP_ORR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	384 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	385
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	386 uint32_t orri_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	388 return data_proci(code, cc, OP_ORR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	389 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	390
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	391 uint32_t mov(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	392 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	393 return data_proc(code, CC_AL, OP_MOV, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	394 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	395
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	396 uint32_t movi(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	397 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 return data_proci(code, CC_AL, OP_MOV, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	399 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	400
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	401 uint32_t mov_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	402 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	403 return data_proc(code, cc, OP_MOV, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	404 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	405
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 uint32_t movi_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	407 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	408 return data_proci(code, cc, OP_MOV, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	409 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	410
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	411 uint32_t bic(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	412 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	413 return data_proc(code, CC_AL, OP_BIC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	414 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	415
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	416 uint32_t bici(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	418 return data_proci(code, CC_AL, OP_BIC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	419 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	420
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 uint32_t bic_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	423 return data_proc(code, cc, OP_BIC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	424 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	425
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	426 uint32_t bici_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	427 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	428 return data_proci(code, cc, OP_BIC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	429 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	430
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	431 uint32_t mvn(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	432 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	433 return data_proc(code, CC_AL, OP_MVN, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	434 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	435
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	436 uint32_t mvni(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	437 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	438 return data_proci(code, CC_AL, OP_MVN, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	439 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	440
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	441 uint32_t mvn_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	442 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	443 return data_proc(code, cc, OP_MVN, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	444 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	445
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	446 uint32_t mvni_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 return data_proci(code, cc, OP_MVN, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	449 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	450
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	451 uint32_t branchi(code_info code, uint32_t cc, uint32_t op, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	452 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	453 uint32_t * from = code->cur + 2;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	454 if (dst - from >= 0x400000 && from - dst > 0x400000) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	455 return INVALID_IMMED;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	456 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	457 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	458 *(code->cur++) = cc \| op \| ((dst - from) & 0xFFFFFF);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	459 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	460 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	461
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	462 uint32_t b(code_info code, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	463 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	464 return branchi(code, CC_AL, OP_B, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	465 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	466
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	467 uint32_t b_cc(code_info code, uint32_t dst, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	468 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	469 return branchi(code, cc, OP_B, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	470 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	471
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	472 uint32_t bl(code_info code, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	474 return branchi(code, CC_AL, OP_BL, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	475 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	476
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	477 uint32_t bl_cc(code_info code, uint32_t dst, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	478 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	479 return branchi(code, cc, OP_BL, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	480 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	481
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	482 uint32_t bx(code_info *code, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	483 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	485 *(code->cur++) = CC_AL \| OP_BX \| dst;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	486 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	487 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	488
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	489 uint32_t bx_cc(code_info *code, uint32_t dst, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	490 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	491 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	492 *(code->cur++) = cc \| OP_BX \| dst;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	493 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	494 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	495
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	496 uint32_t push(code_info *code, uint32_t reg)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	497 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	498 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	499 *(code->cur++) = CC_AL \| PUSH \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	500 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	501 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	502
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	503 uint32_t push_cc(code_info *code, uint32_t reg, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	504 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	505 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	506 *(code->cur++) = cc \| PUSH \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	507 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	508 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	509
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	510 uint32_t pushm(code_info *code, uint32_t reglist)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	511 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	512 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	513 *(code->cur++) = CC_AL \| PUSHM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	514 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	515 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	516
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	517 uint32_t pushm_cc(code_info *code, uint32_t reglist, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	519 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	520 *(code->cur++) = cc \| PUSHM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	521 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	522 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	523
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	524 uint32_t pop(code_info *code, uint32_t reg)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	525 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	526 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	527 *(code->cur++) = CC_AL \| POP \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	528 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	529 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	530
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	531 uint32_t pop_cc(code_info *code, uint32_t reg, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	532 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	533 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	534 *(code->cur++) = cc \| POP \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	535 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	536 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	537
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	538 uint32_t popm(code_info *code, uint32_t reglist)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	539 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	540 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	541 *(code->cur++) = CC_AL \| POPM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	542 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	543 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	544
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	545 uint32_t popm_cc(code_info *code, uint32_t reglist, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	546 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	547 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	548 *(code->cur++) = cc \| POPM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	549 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	550 }

Mercurial > repos > blastem

annotate gen_arm.c @ 563:c8fefa140c80