repos/blastem: gen_arm.c annotate

annotate gen_arm.c @ 1637:95880d947257

Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order

author	Michael Pavone <pavone@retrodev.com>
date	Sun, 11 Nov 2018 22:39:29 -0800
parents	724bbec47f86
children

rev	line source
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 /*
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 Copyright 2014 Michael Pavone
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 This file is part of BlastEm.
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 */
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "gen_arm.h"
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "mem.h"
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include <stdio.h>
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <stdlib.h>
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	10
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define OP_FIELD_SHIFT 21u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	12
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 //Data processing format instructions
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 #define OP_AND 0x0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define OP_EOR (0x1u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define OP_SUB (0x2u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define OP_RSB (0x3u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define OP_ADD (0x4u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define OP_ADC (0x5u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define OP_SBC (0x6u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 #define OP_RSC (0x7u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 #define OP_TST (0x8u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 #define OP_TEQ (0x9u << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 #define OP_CMP (0xAu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 #define OP_CMN (0xBu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 #define OP_ORR (0xCu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 #define OP_MOV (0xDu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 #define OP_BIC (0xEu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 #define OP_MVN (0xFu << OP_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	30
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 //branch instructions
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 #define OP_B 0xA000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 #define OP_BL 0xB000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 #define OP_BX 0x12FFF10u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	35
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 //load/store
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 #define OP_STR 0x4000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 #define OP_LDR 0x4100000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 #define OP_STM 0x8000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 #define OP_LDM 0x8100000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 #define POST_IND 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 #define PRE_IND 0x1000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 #define DIR_DOWN 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 #define DIR_UP 0x0800000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 #define SZ_W 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 #define SZ_B 0x0400000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 #define WRITE_B 0x0200000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 #define OFF_IMM 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 #define OFF_REG 0x2000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	50
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 #define PUSH (OP_STR \| PRE_IND \| OFF_IMM \| SZ_W \| WRITE_B \| DIR_DOWN \| sizeof(uint32_t) \| (sp << 16))
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 #define POP (OP_LDR \| POST_IND \| OFF_IMM \| SZ_W \| DIR_UP \| sizeof(uint32_t) \| (sp << 16))
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 #define PUSHM (OP_STM \| PRE_IND \| SZ_W \| WRITE_B \| DIR_DOWN \| (sp << 16))
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	54 #define POPM (OP_LDM \| POST_IND \| SZ_W \| WRITE_B \| DIR_UP \| (sp << 16))
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	55
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 #define IMMED 0x2000000u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 #define REG 0u
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	58
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	59
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 uint32_t make_immed(uint32_t val)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 uint32_t rot_amount = 0;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 for (; rot_amount < 0x20; rot_amount += 2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 uint32_t test_mask = ~(0xFF << rot_amount \| 0xFF >> (32-rot_amount));
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 if (!(test_mask & val)) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 return val << rot_amount \| val >> (32-rot_amount) \| rot_amount << 7;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 return INVALID_IMMED;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	72
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 void check_alloc_code(code_info *code)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 {
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	75 if (code->cur == code->last) {
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 size_t size = CODE_ALLOC_SIZE;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 uint32_t *next_code = alloc_code(&size);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 if (!next_code) {
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 684 diff changeset	79 fatal_error("Failed to allocate memory for generated code\n");
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 }
563 c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic Michael Pavone <pavone@retrodev.com> parents: 554 diff changeset	81 if (next_code = code->last + RESERVE_WORDS) {
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 //new chunk is contiguous with the current one
563 c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic Michael Pavone <pavone@retrodev.com> parents: 554 diff changeset	83 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS;
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 } else {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 uint32_t * from = code->cur + 2;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 if (next_code - from < 0x400000 \|\| from - next_code <= 0x400000) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 *from = CC_AL \| OP_B \| ((next_code - from) & 0xFFFFFF);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 } else {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 //push r0 onto the stack
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 *(from++) = CC_AL \| PUSH;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 uint32_t immed = make_immed((uint32_t)next_code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 if (immed == INVALID_IMMED) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 //Load target into r0 from word after next instruction into register 0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 *(from++) = CC_AL \| OP_LDR \| OFF_IMM \| DIR_DOWN \| PRE_IND \| SZ_W \| (pc << 16) \| 4;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 from[1] = (uint32_t)next_code;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 } else {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 //Load target into r0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 *(from++) = CC_AL \| OP_MOV \| IMMED \| NO_COND \| immed;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 //branch to address in r0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 *from = CC_AL \| OP_BX;
563 c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic Michael Pavone <pavone@retrodev.com> parents: 554 diff changeset	102 code->last = next_code + size/sizeof(code_word) - RESERVE_WORDS;
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 //pop r0
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 *(next_code++) = CC_AL \| POP;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 code->cur = next_code;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	110
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 uint32_t data_proc(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 check_alloc_code(code);
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	114 *(code->cur++) = cond \| op \| set_cond \| (src1 << 16) \| (dst << 12) \| src2;
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	115
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	118
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 uint32_t data_proci(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	120 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 immed = make_immed(immed);
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	122 if (immed == INVALID_IMMED) {
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 return immed;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 }
554 474270dbff15 Fix ARM code generation and test program Michael Pavone <pavone@retrodev.com> parents: 553 diff changeset	125 return data_proc(code, cond, op \| IMMED, set_cond, dst, src1, immed);
553 1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	127
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 //TODO: support shifted register for op2
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	129
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 return data_proc(code, CC_AL, OP_AND, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	134
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	135 uint32_t andi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 return data_proci(code, CC_AL, OP_AND, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	139
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	140 uint32_t and_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 return data_proc(code, cc, OP_AND, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	144
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	145 uint32_t andi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 return data_proci(code, cc, OP_AND, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	149
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 uint32_t eor(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 return data_proc(code, CC_AL, OP_EOR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	154
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 uint32_t eori(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 return data_proci(code, CC_AL, OP_EOR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	159
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	160 uint32_t eor_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 return data_proc(code, cc, OP_EOR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	164
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 uint32_t eori_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 return data_proci(code, cc, OP_EOR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	169
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 uint32_t sub(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 return data_proc(code, CC_AL, OP_SUB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	174
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 uint32_t subi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 return data_proci(code, CC_AL, OP_SUB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	179
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 uint32_t sub_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 return data_proc(code, cc, OP_SUB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	184
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 uint32_t subi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 return data_proci(code, cc, OP_SUB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	189
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 uint32_t rsb(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 return data_proc(code, CC_AL, OP_RSB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	194
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 uint32_t rsbi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 return data_proci(code, CC_AL, OP_RSB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	199
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 uint32_t rsb_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 return data_proc(code, cc, OP_RSB, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	204
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 uint32_t rsbi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 return data_proci(code, cc, OP_RSB, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	209
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 uint32_t add(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 return data_proc(code, CC_AL, OP_ADD, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	214
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 uint32_t addi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	217 return data_proci(code, CC_AL, OP_ADD, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	219
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 uint32_t add_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 return data_proc(code, cc, OP_ADD, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	224
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 uint32_t addi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 return data_proci(code, cc, OP_ADD, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	229
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	230 uint32_t adc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 return data_proc(code, CC_AL, OP_ADC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	234
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 uint32_t adci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 return data_proci(code, CC_AL, OP_ADC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	239
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 uint32_t adc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 return data_proc(code, cc, OP_ADC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	244
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 uint32_t adci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 return data_proci(code, cc, OP_ADC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	249
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 uint32_t sbc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	252 return data_proc(code, CC_AL, OP_SBC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	254
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 uint32_t sbci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 return data_proci(code, CC_AL, OP_SBC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	259
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 uint32_t sbc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 return data_proc(code, cc, OP_SBC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	264
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 uint32_t sbci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 return data_proci(code, cc, OP_SBC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	269
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 uint32_t rsc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 return data_proc(code, CC_AL, OP_RSC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	274
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 uint32_t rsci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 return data_proci(code, CC_AL, OP_RSC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	279
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 uint32_t rsc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 return data_proc(code, cc, OP_RSC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	284
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 uint32_t rsci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 return data_proci(code, cc, OP_RSC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	289
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 uint32_t tst(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 return data_proc(code, CC_AL, OP_TST, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	294
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 uint32_t tsti(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 return data_proci(code, CC_AL, OP_TST, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	299
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 uint32_t tst_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 return data_proc(code, cc, OP_TST, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	304
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 uint32_t tsti_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 return data_proci(code, cc, OP_TST, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	309
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	310 uint32_t teq(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 return data_proc(code, CC_AL, OP_TEQ, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	313 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	314
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 uint32_t teqi(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 return data_proci(code, CC_AL, OP_TEQ, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	318 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	319
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 uint32_t teq_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	321 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	322 return data_proc(code, cc, OP_TEQ, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	324
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	325 uint32_t teqi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	326 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 return data_proci(code, cc, OP_TEQ, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	328 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	329
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	330 uint32_t cmp(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 return data_proc(code, CC_AL, OP_CMP, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	333 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	334
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 uint32_t cmpi(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	336 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 return data_proci(code, CC_AL, OP_CMP, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	339
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 uint32_t cmp_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 return data_proc(code, cc, OP_CMP, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	343 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	344
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 uint32_t cmpi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	347 return data_proci(code, cc, OP_CMP, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	348 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	349
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 uint32_t cmn(code_info *code, uint32_t src1, uint32_t src2)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	351 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 return data_proc(code, CC_AL, OP_CMN, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	354
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	355 uint32_t cmni(code_info *code, uint32_t src1, uint32_t immed)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 return data_proci(code, CC_AL, OP_CMN, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	358 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	359
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 uint32_t cmn_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 return data_proc(code, cc, OP_CMN, SET_COND, r0, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	364
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	365 uint32_t cmni_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 return data_proci(code, cc, OP_CMN, SET_COND, r0, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	369
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 uint32_t orr(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 return data_proc(code, CC_AL, OP_ORR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	374
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 uint32_t orri(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 return data_proci(code, CC_AL, OP_ORR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	379
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 uint32_t orr_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	381 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	382 return data_proc(code, cc, OP_ORR, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	384
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	385 uint32_t orri_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	386 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 return data_proci(code, cc, OP_ORR, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	388 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	389
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	390 uint32_t mov(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	391 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	392 return data_proc(code, CC_AL, OP_MOV, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	393 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	394
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	395 uint32_t movi(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	396 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	397 return data_proci(code, CC_AL, OP_MOV, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	399
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	400 uint32_t mov_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	401 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	402 return data_proc(code, cc, OP_MOV, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	403 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	404
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 uint32_t movi_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	407 return data_proci(code, cc, OP_MOV, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	408 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	409
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	410 uint32_t bic(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	411 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	412 return data_proc(code, CC_AL, OP_BIC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	413 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	414
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	415 uint32_t bici(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	416 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 return data_proci(code, CC_AL, OP_BIC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	418 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	419
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 uint32_t bic_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 return data_proc(code, cc, OP_BIC, set_cond, dst, src1, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	423 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	424
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	425 uint32_t bici_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	426 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	427 return data_proci(code, cc, OP_BIC, set_cond, dst, src1, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	428 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	429
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	430 uint32_t mvn(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	431 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	432 return data_proc(code, CC_AL, OP_MVN, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	433 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	434
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	435 uint32_t mvni(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	436 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	437 return data_proci(code, CC_AL, OP_MVN, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	438 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	439
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	440 uint32_t mvn_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	441 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	442 return data_proc(code, cc, OP_MVN, set_cond, dst, 0, src2);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	443 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	444
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	445 uint32_t mvni_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	446 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 return data_proci(code, cc, OP_MVN, set_cond, dst, 0, immed);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	449
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	450 uint32_t branchi(code_info code, uint32_t cc, uint32_t op, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	451 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	452 uint32_t * from = code->cur + 2;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	453 if (dst - from >= 0x400000 && from - dst > 0x400000) {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	454 return INVALID_IMMED;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	455 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	456 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	457 *(code->cur++) = cc \| op \| ((dst - from) & 0xFFFFFF);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	458 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	459 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	460
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	461 uint32_t b(code_info code, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	462 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	463 return branchi(code, CC_AL, OP_B, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	464 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	465
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	466 uint32_t b_cc(code_info code, uint32_t dst, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	467 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	468 return branchi(code, cc, OP_B, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	469 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	470
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	471 uint32_t bl(code_info code, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	472 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 return branchi(code, CC_AL, OP_BL, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	474 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	475
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	476 uint32_t bl_cc(code_info code, uint32_t dst, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	477 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	478 return branchi(code, cc, OP_BL, dst);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	479 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	480
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	481 uint32_t bx(code_info *code, uint32_t dst)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	482 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	483 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 *(code->cur++) = CC_AL \| OP_BX \| dst;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	485 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	486 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	487
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	488 uint32_t bx_cc(code_info *code, uint32_t dst, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	489 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	490 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	491 *(code->cur++) = cc \| OP_BX \| dst;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	492 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	493 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	494
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	495 uint32_t push(code_info *code, uint32_t reg)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	496 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	497 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	498 *(code->cur++) = CC_AL \| PUSH \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	499 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	500 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	501
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	502 uint32_t push_cc(code_info *code, uint32_t reg, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	503 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	504 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	505 *(code->cur++) = cc \| PUSH \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	506 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	507 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	508
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	509 uint32_t pushm(code_info *code, uint32_t reglist)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	510 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	511 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	512 *(code->cur++) = CC_AL \| PUSHM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	513 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	514 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	515
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	516 uint32_t pushm_cc(code_info *code, uint32_t reglist, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	517 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	519 *(code->cur++) = cc \| PUSHM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	520 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	521 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	522
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	523 uint32_t pop(code_info *code, uint32_t reg)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	524 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	525 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	526 *(code->cur++) = CC_AL \| POP \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	527 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	528 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	529
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	530 uint32_t pop_cc(code_info *code, uint32_t reg, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	531 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	532 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	533 *(code->cur++) = cc \| POP \| reg << 12;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	534 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	535 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	536
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	537 uint32_t popm(code_info *code, uint32_t reglist)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	538 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	539 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	540 *(code->cur++) = CC_AL \| POPM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	541 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	542 }
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	543
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	544 uint32_t popm_cc(code_info *code, uint32_t reglist, uint32_t cc)
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	545 {
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	546 check_alloc_code(code);
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	547 *(code->cur++) = cc \| POPM \| reglist;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	548 return CODE_OK;
1af6c1052993 Added untested code for generating ARM machine code Mike Pavone <pavone@retrodev.com> parents: diff changeset	549 }
684 bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	550
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	551 uint32_t load_store_immoff(code_info *code, uint32_t op, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc)
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	552 {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	553 if (offset >= 0x1000 \|\| offset <= -0x1000) {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	554 return INVALID_IMMED;
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	555 }
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	556 check_alloc_code(code);
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	557 uint32_t instruction = cc \| op \| POST_IND \| OFF_IMM \| SZ_W \| base << 16 \| dst << 12;
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	558 if (offset >= 0) {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	559 instruction \|= offset \| DIR_UP;
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	560 } else {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	561 instruction \|= (-offset) \| DIR_DOWN;
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	562 }
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	563 *(code->cur++) = instruction;
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	564 return CODE_OK;
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	565 }
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	566
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	567 uint32_t ldr_cc(code_info *code, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc)
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	568 {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	569 return load_store_immoff(code, OP_LDR, dst, base, offset, cc);
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	570 }
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	571
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	572 uint32_t ldr(code_info *code, uint32_t dst, uint32_t base, int32_t offset)
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	573 {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	574 return ldr_cc(code, dst, base, offset, CC_AL);
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	575 }
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	576
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	577 uint32_t str_cc(code_info *code, uint32_t src, uint32_t base, int32_t offset, uint32_t cc)
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	578 {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	579 return load_store_immoff(code, OP_STR, src, base, offset, cc);
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	580 }
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	581
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	582 uint32_t str(code_info *code, uint32_t src, uint32_t base, int32_t offset)
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	583 {
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	584 return str_cc(code, src, base, offset, CC_AL);
bff307e03a94 Added ldr and str instructions to gen_arm Michael Pavone <pavone@retrodev.com> parents: 563 diff changeset	585 }

Mercurial > repos > blastem

annotate gen_arm.c @ 1637:95880d947257