Mercurial > repos > blastem
annotate ymz263b.c @ 2460:a4f8fa24764b
Initial work on emulating the YMZ263B in the Copera
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 23 Feb 2024 01:16:38 -0800 |
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children | a25e8f304343 |
rev | line source |
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2460
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Initial work on emulating the YMZ263B in the Copera
Michael Pavone <pavone@retrodev.com>
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1 #include <string.h> |
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2 #include "ymz263b.h" |
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3 #include "backend.h" |
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4 |
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5 enum { |
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6 YMZ_SELT, |
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7 YMZ_LSI_TEST, |
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8 YMZ_TIMER0_LOW, |
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9 YMZ_TIMER0_HIGH, |
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10 YMZ_TIMER_BASE, |
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11 YMZ_TIMER1, |
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12 YMZ_TIMER2_LOW, |
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13 YMZ_TIMER2_HIGH, |
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14 YMZ_TIMER_CTRL, |
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15 YMZ_PCM_PLAY_CTRL, |
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16 YMZ_PCM_VOL, |
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17 YMZ_PCM_DATA, |
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18 YMZ_PCM_CTRL, |
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19 YMZ_MIDI_CTRL, |
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20 YMZ_MIDI_DATA |
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21 }; |
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22 |
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23 //YMZ_SELT |
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24 #define BIT_SELT 0x01 |
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25 |
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26 //YMZ_TIMER_CTRL |
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27 #define BIT_ST0 0x01 |
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28 #define BIT_ST1 0x02 |
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29 #define BIT_ST2 0x04 |
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30 #define BIT_STBC 0x08 |
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31 #define BIT_T0_MSK 0x10 |
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32 #define BIT_T1_MSK 0x20 |
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33 #define BIT_T2_MSK 0x40 |
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34 |
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35 #define TIMER_RUN_MASK (BIT_ST0|BIT_ST1|BIT_ST2) |
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36 #define TIMER_INT_MASK (BIT_T0_MSK|BIT_T1_MSK|BIT_T2_MSK) |
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37 |
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38 //YMZ_PCM_PLAY_CTRL |
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39 #define BIT_ADP_RST 0x80 |
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40 |
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41 //YMZ_MIDI_CTRL |
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42 #define BIT_MSK_RRQ 0x01 |
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43 #define BIT_MRC_RST 0x02 |
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44 #define BIT_MSK_TRQ 0x04 |
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45 #define BIT_MTR_RST 0x08 |
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46 #define BIT_MSK_MOV 0x10 |
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47 #define BIT_MSK_POV 0x20 |
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48 |
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49 #define STATUS_FIF1 0x01 |
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50 #define STATUS_FIF2 0x02 |
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51 #define STATUS_RRQ 0x04 |
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52 #define STATUS_TRQ 0x08 |
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53 #define STATUS_T0 0x10 |
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54 #define STATUS_T1 0x20 |
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55 #define STATUS_T2 0x40 |
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56 #define STATUS_OV 0x80 |
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57 |
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58 #define MIDI_BYTE_DIVIDER 170 |
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59 |
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60 #define FIFO_EMPTY 255 |
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61 void ymz263b_init(ymz263b *ymz, uint32_t clock_divider) |
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62 { |
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63 memset(ymz, 0, sizeof(*ymz)); |
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64 ymz->clock_inc = clock_divider * 32; |
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65 ymz->base_regs[YMZ_SELT] = 1; |
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66 ymz->pcm[0].regs[0] = BIT_ADP_RST; |
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67 ymz->pcm[1].regs[0] = BIT_ADP_RST; |
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68 ymz->midi_regs[0] = BIT_MTR_RST | BIT_MRC_RST; |
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69 ymz->midi_trs.read = ymz->midi_rcv.read = FIFO_EMPTY; |
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70 ymz->status = 0; |
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71 } |
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72 |
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73 static uint8_t fifo_empty(ymz_midi_fifo *fifo) |
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74 { |
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75 return fifo->read == FIFO_EMPTY; |
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76 } |
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77 |
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78 static uint8_t fifo_read(ymz_midi_fifo *fifo) |
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79 { |
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80 uint8_t ret = fifo->fifo[fifo->read++]; |
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81 fifo->read &= 15; |
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82 if (fifo->read == fifo->write) { |
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83 fifo->read = FIFO_EMPTY; |
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84 } |
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85 return ret; |
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86 } |
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87 |
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88 static uint8_t fifo_write(ymz_midi_fifo *fifo, uint8_t value) |
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89 { |
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90 uint8_t overflow = fifo->read == fifo->write; |
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91 if (fifo->read == FIFO_EMPTY) { |
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92 fifo->read = fifo->write; |
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93 } |
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94 fifo->fifo[fifo->write++] = value; |
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95 fifo->write &= 15; |
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96 return overflow; |
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97 } |
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98 |
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99 static uint8_t fifo_size(ymz_midi_fifo *fifo) |
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100 { |
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101 if (fifo->read == FIFO_EMPTY) { |
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102 return 0; |
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103 } |
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104 if (fifo->read == fifo->write) { |
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105 return 16; |
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106 } |
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107 return (fifo->write - fifo->read) & 15; |
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108 } |
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109 |
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110 void ymz263b_run(ymz263b *ymz, uint32_t target_cycle) |
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111 { |
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112 uint8_t timer_ctrl = ymz->base_regs[YMZ_TIMER_CTRL]; |
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113 for (; ymz->cycle < target_cycle; ymz->cycle += ymz->clock_inc) |
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114 { |
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115 if (timer_ctrl & BIT_ST0) { |
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116 if (ymz->timers[0]) { |
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117 ymz->timers[0]--; |
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118 } else { |
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119 ymz->timers[0] = ymz->base_regs[YMZ_TIMER0_HIGH] << 8 | ymz->base_regs[YMZ_TIMER0_LOW]; |
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120 ymz->status |= STATUS_T0; |
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121 } |
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122 } |
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123 if (timer_ctrl & BIT_STBC) { |
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124 if (ymz->timers[3]) { |
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125 ymz->timers[3]--; |
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126 } else { |
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127 ymz->timers[3] = ymz->base_regs[YMZ_TIMER1] << 8 & 0xF00; |
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128 ymz->timers[3] |= ymz->base_regs[YMZ_TIMER_BASE]; |
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129 |
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130 if (timer_ctrl & BIT_ST1) { |
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131 if (ymz->timers[1]) { |
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132 ymz->timers[1]--; |
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133 } else { |
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134 ymz->timers[1] = ymz->base_regs[YMZ_TIMER1] >> 4; |
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135 ymz->status |= STATUS_T1; |
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136 } |
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137 } |
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138 |
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139 if (timer_ctrl & BIT_ST2) { |
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140 if (ymz->timers[2]) { |
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141 ymz->timers[2]--; |
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142 } else { |
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143 ymz->timers[2] = ymz->base_regs[YMZ_TIMER2_HIGH] << 8 | ymz->base_regs[YMZ_TIMER2_LOW]; |
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144 ymz->status |= STATUS_T2; |
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145 } |
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146 } |
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147 } |
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148 } |
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149 if (!(ymz->midi_regs[0] & BIT_MTR_RST) && !fifo_empty(&ymz->midi_trs)) { |
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150 if (ymz->midi_transmit) { |
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151 --ymz->midi_transmit; |
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152 } else { |
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153 ymz->midi_transmit = MIDI_BYTE_DIVIDER - 1; |
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154 //TODO: send this byte to MIDI device |
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155 uint8_t byte = fifo_read(&ymz->midi_trs); |
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156 printf("MIDI Transmit: %X\n", byte); |
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157 if (fifo_empty(&ymz->midi_trs)) { |
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158 ymz->status |= STATUS_TRQ; |
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159 } |
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160 } |
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161 } |
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162 } |
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163 } |
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164 |
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165 uint32_t ymz263b_next_int(ymz263b *ymz) |
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166 { |
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167 //TODO: Handle FIFO and MIDI receive interrupts |
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168 uint8_t enabled_ints = (~ymz->base_regs[YMZ_TIMER_CTRL]) & TIMER_INT_MASK; |
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169 if (!(ymz->base_regs[YMZ_MIDI_CTRL] & (BIT_MTR_RST|BIT_MSK_TRQ))) { |
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170 enabled_ints |= STATUS_TRQ; |
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171 } |
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172 if (!enabled_ints) { |
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173 return CYCLE_NEVER; |
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174 } |
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175 //Handle currently pending interrupts |
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176 if (enabled_ints & ymz->status) { |
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177 return ymz->cycle; |
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178 } |
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179 uint32_t ret = CYCLE_NEVER; |
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180 if (enabled_ints & STATUS_TRQ) { |
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181 uint8_t bytes = fifo_size(&ymz->midi_trs); |
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182 if (bytes) { |
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183 ret = ymz->cycle + (ymz->midi_transmit + 1) * ymz->clock_inc; |
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184 if (bytes > 1) { |
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185 ret += MIDI_BYTE_DIVIDER * ymz->clock_inc * (bytes - 1); |
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186 } |
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187 } |
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188 } |
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189 enabled_ints >>= 4; |
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190 //If timers aren't already expired, interrupts can't fire unless the timers are enabled |
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191 enabled_ints &= ymz->base_regs[YMZ_TIMER_CTRL]; |
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192 if (!(ymz->base_regs[YMZ_TIMER_CTRL] & BIT_STBC)) { |
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193 //Timer 1 and Timer 2 depend on the base timer |
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194 enabled_ints &= 1; |
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195 } |
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196 if (enabled_ints & BIT_ST0) { |
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197 uint32_t t0 = ymz->cycle + (ymz->timers[0] + 1) * ymz->clock_inc; |
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198 if (t0 < ret) { |
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199 ret = t0; |
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200 } |
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201 } |
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202 if (enabled_ints & (BIT_ST1|BIT_ST2)) { |
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203 uint32_t base = ymz->cycle + (ymz->timers[3] + 1) * ymz->clock_inc; |
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204 if (base < ret) { |
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205 uint32_t load = (ymz->base_regs[YMZ_TIMER1] << 8 & 0xF00) | ymz->base_regs[YMZ_TIMER_BASE]; |
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206 if (enabled_ints & BIT_ST1) { |
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207 uint32_t t1 = ymz->timers[1] * (load + 1) * ymz->clock_inc; |
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208 if (t1 < ret) { |
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209 ret = t1; |
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210 } |
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211 } |
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212 if (enabled_ints & BIT_ST2) { |
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213 uint32_t t2 = ymz->timers[2] * (load + 1) * ymz->clock_inc; |
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214 if (t2 < ret) { |
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215 ret = t2; |
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216 } |
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217 } |
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218 } |
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219 } |
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220 return ret; |
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221 } |
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222 |
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223 void ymz263b_address_write(ymz263b *ymz, uint8_t value) |
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224 { |
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225 ymz->address = value; |
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226 } |
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227 |
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228 void ymz263b_data_write(ymz263b *ymz, uint32_t channel, uint8_t value) |
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229 { |
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230 if (channel) { |
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231 if (ymz->address >= YMZ_PCM_PLAY_CTRL && ymz->address < YMZ_MIDI_CTRL) { |
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232 ymz->pcm[1].regs[ymz->address - YMZ_PCM_PLAY_CTRL] = value; |
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233 } |
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234 } else { |
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235 if (ymz->address < YMZ_PCM_PLAY_CTRL) { |
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236 ymz->base_regs[ymz->address] = value; |
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237 } else if (ymz->address < YMZ_MIDI_CTRL) { |
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238 ymz->pcm[0].regs[ymz->address - YMZ_PCM_PLAY_CTRL] = value; |
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239 } else { |
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240 ymz->midi_regs[ymz->address - YMZ_MIDI_CTRL] = value; |
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241 if (ymz->address == YMZ_MIDI_DATA) { |
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242 ymz->status &= ~STATUS_TRQ; |
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243 if (fifo_empty(&ymz->midi_trs)) { |
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244 ymz->midi_transmit = MIDI_BYTE_DIVIDER - 1; |
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245 } |
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246 fifo_write(&ymz->midi_trs, value); |
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247 } |
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248 } |
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249 } |
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250 } |
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251 |
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252 uint8_t ymz263b_data_read(ymz263b *ymz, uint32_t channel) |
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253 { |
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254 //TODO: Supposedly only a few registers are actually readable |
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255 if (channel) { |
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256 if (ymz->address >= YMZ_PCM_PLAY_CTRL && ymz->address < YMZ_MIDI_CTRL) { |
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257 return ymz->pcm[1].regs[ymz->address - YMZ_PCM_PLAY_CTRL]; |
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258 } |
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259 } else { |
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260 if (ymz->address < YMZ_PCM_PLAY_CTRL) { |
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261 return ymz->base_regs[ymz->address]; |
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262 } else if (ymz->address < YMZ_MIDI_CTRL) { |
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263 return ymz->pcm[0].regs[ymz->address - YMZ_PCM_PLAY_CTRL]; |
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264 } else { |
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265 return ymz->midi_regs[ymz->address - YMZ_MIDI_CTRL]; |
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266 } |
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267 } |
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268 return 0XFF; |
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269 } |
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270 |
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271 uint8_t ymz263b_status_read(ymz263b *ymz) |
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272 { |
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273 uint8_t ret = ymz->status; |
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274 ymz->status = 0;//&= ~(STATUS_T0|STATUS_T1|STATUS_T2); |
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275 return ret; |
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276 } |