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annotate upd78k2_util.c @ 2713:a88eff3fb5d8

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Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
author Michael Pavone <pavone@retrodev.com>
date Thu, 10 Jul 2025 16:07:04 -0700
parents 0bd48217941a
children d30e7f605ff8
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2705
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1 #include <string.h>
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2
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3 void upd78k2_read_8(upd78k2_context *upd)
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4 {
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5 uint32_t tmp = upd->scratch1;
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6 upd->scratch1 = read_byte(upd->scratch1, (void **)upd->mem_pointers, &upd->opts->gen, upd);
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7 if (tmp == upd->pc) {
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8 printf("uPD78K/II fetch %04X: %02X, AX=%02X%02X BC=%02X%02X DE=%02X%02X HL=%02X%02X SP=%04X\n", tmp, upd->scratch1,
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9 upd->main[1], upd->main[0], upd->main[3], upd->main[2], upd->main[5], upd->main[4], upd->main[7], upd->main[6], upd->sp);
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10 }
2713
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11 //FIXME: cycle count
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12 upd->cycles += 2 * upd->opts->gen.clock_divider;
2705
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13 }
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14
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15 void upd78k2_write_8(upd78k2_context *upd)
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16 {
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17 write_byte(upd->scratch2, upd->scratch1, (void **)upd->mem_pointers, &upd->opts->gen, upd);
2713
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18 //FIXME: cycle count
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19 upd->cycles += 2 * upd->opts->gen.clock_divider;
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20 }
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21
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22 #define CE0 0x08
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23 #define CE1 0x08
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24 #define CIF00 0x0010
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25 #define CIF01 0x0020
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26 #define CIF10 0x0040
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27 #define CIF11 0x0080
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28
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29 void upd78k2_update_timer0(upd78k2_context *upd)
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30 {
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31 uint32_t diff = (upd->cycles - upd->tm0_cycle) / upd->opts->gen.clock_divider;
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32 upd->tm0_cycle += (diff & ~7) * upd->opts->gen.clock_divider;
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33 diff >>= 3;
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34 if (upd->tmc0 & CE0) {
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35 uint32_t tmp = upd->tm0 + diff;
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36 //TODO: the rest of the CR00/CR01 stuff
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37 if (upd->tm0 < upd->cr00 && tmp >= upd->cr00) {
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38 upd->if0 |= CIF00;
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39 }
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40 if (upd->tm0 < upd->cr01 && tmp >= upd->cr01) {
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41 upd->if0 |= CIF01;
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42 if (upd->crc0 & 8) {
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43 //CR01 clear is enabled
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44 if (upd->cr01) {
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45 while (tmp >= upd->cr01) {
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46 tmp -= upd->cr01;
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47 }
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48 } else {
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49 tmp = 0;
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50 }
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51 }
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52 }
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53 if (tmp > 0xFFFF) {
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54 upd->tmc0 |= 4;
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55 }
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56 upd->tm0 = tmp;
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57 }
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58 }
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59
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60 uint8_t upd78k2_tm1_scale(upd78k2_context *upd)
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61 {
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62 uint8_t scale = upd->prm1 & 3;
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63 if (scale < 2) {
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64 scale = 2;
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65 }
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66 scale++;
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67 return scale;
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68 }
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69
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70 void upd78k2_update_timer1(upd78k2_context *upd)
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71 {
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72 uint8_t scale = upd78k2_tm1_scale(upd);
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73 uint32_t diff = (upd->cycles - upd->tm1_cycle) / upd->opts->gen.clock_divider;
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74 upd->tm1_cycle += (diff & ~((1 << scale) - 1)) * upd->opts->gen.clock_divider;
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75 diff >>= scale;
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76 if (upd->tmc1 & CE1) {
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77 //tm1 count enabled
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78 uint32_t tmp = upd->tm1 + diff;
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79 if (upd->tm1 < upd->cr10 && tmp >= upd->cr10) {
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80 upd->if0 |= CIF10;
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81 }
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82 if (upd->tm1 < upd->cr11 && tmp >= upd->cr11) {
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83 upd->if0 |= CIF11;
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84 }
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85 uint8_t do_clr11 = 0;
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86 if (upd->crc1 & 2) {
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87 //clr10 enabled
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88 uint8_t do_clr10 = 1;
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89 if ((upd->crc1 & 0xC) == 8) {
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90 //clr11 also enabled
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91 if (upd->cr11 < upd->cr10) {
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92 do_clr10 = 0;
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93 do_clr11 = 1;
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94
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95 }
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96 }
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97 if (do_clr10) {
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98 if (upd->cr10) {
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99 while (tmp >= upd->cr10) {
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100 tmp -= upd->cr10;
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101 }
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102 } else {
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103 tmp = 0;
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104 }
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105 }
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106 } else if ((upd->crc1 & 0xC) == 8) {
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107 do_clr11 = 1;
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108 }
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109 if (do_clr11) {
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110 if (upd->cr11) {
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111 while (tmp >= upd->cr11) {
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112 tmp -= upd->cr11;
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113 }
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114 } else {
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115 tmp = 0;
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116 }
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117 }
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118 if (tmp > 0xFF) {
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119 upd->tmc1 |= 4;
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diff changeset
120 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
121 upd->tm1 = tmp;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
122 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
123 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
124
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
125 #define CMK00 CIF00
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
126 #define CMK01 CIF01
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
127 #define CMK10 CIF10
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
128 #define CMK11 CIF11
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
129
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
130 void upd78k2_calc_next_int(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
131 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
132 uint32_t next_int = 0xFFFFFFFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
133 if (!upd->int_enable) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
134 //maskable interrupts disabled
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
135 //TODO: NMIs
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
136 upd->int_cycle = next_int;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
137 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
138 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
139 if (upd->if0 & (~upd->mk0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
140 //unmasked interrupt is pending
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
141 upd->int_cycle = upd->cycles;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
142 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
143 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
144 uint32_t cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
145 if (!(upd->mk0 & CMK00) && (upd->tmc0 & CE0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
146 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
147 cycle = ((uint16_t)(upd->cr00 - upd->tm0)) << 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
148 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
149 cycle += upd->tm0_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
150 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
151 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
152 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
153 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
154 if (!(upd->mk0 & CMK01) && (upd->tmc0 & CE0)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
155 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
156 cycle = ((uint16_t)(upd->cr01 - upd->tm0)) << 3;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
157 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
158 cycle += upd->tm0_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
159 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
160 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
161 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
162 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
163 uint8_t scale = upd78k2_tm1_scale(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
164 if (!(upd->mk0 & CMK10) && (upd->tmc1 & CE1)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
165 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
166 cycle = ((uint8_t)(upd->cr10 - upd->tm1)) << scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
167 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
168 cycle += upd->tm1_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
169 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
170 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
171 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
172 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
173 if (!(upd->mk0 & CMK11) && (upd->tmc1 & CE1)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
174 //TODO: account for clear function
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
175 cycle = ((uint8_t)(upd->cr11 - upd->tm1)) << scale;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
176 cycle *= upd->opts->gen.clock_divider;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
177 cycle += upd->tm1_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
178 if (cycle < next_int) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
179 next_int = cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
180 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
181 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
182 if (next_int != upd->int_cycle) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
183 printf("UPD78K/II int cycle: %u, cur cycle %u\n", next_int, upd->cycles);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
184 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
185 upd->int_cycle = next_int;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188 uint8_t upd78237_sfr_read(uint32_t address, void *context)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 upd78k2_context *upd = context;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191 if (address < 8) {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 return upd->port_data[address];
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194 switch (address)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 case 0x21:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 case 0x26:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 return upd->port_mode[address & 0x7];
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
199 case 0x5D:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
200 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
201 printf("TMC0 Read: %02X\n", upd->tmc0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
202 return upd->tmc0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
203 case 0x5F:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
204 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
205 printf("TMC1 Read: %02X\n", upd->tmc1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
206 return upd->tmc1;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 case 0xC4:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 return upd->mm;
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
209 case 0xE0:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
210 return upd->if0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
211 case 0xE1:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
212 return upd->if0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
213 case 0xE4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
214 return upd->mk0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
215 case 0xE5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
216 return upd->mk0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
217 case 0xE8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
218 return upd->pr0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
219 case 0xE9:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
220 return upd->pr0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
221 case 0xEC:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
222 return upd->ism0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
223 case 0xED:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
224 return upd->ism0 >> 8;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
225 case 0xF4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
226 return upd->intm0;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
227 case 0xF5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
228 return upd->intm1;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
229 case 0xF8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
230 return upd->ist;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 default:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 fprintf(stderr, "Unhandled uPD78237 SFR read %02X\n", address);
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 return 0xFF;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 void *upd78237_sfr_write(uint32_t address, void *context, uint8_t value)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 upd78k2_context *upd = context;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 if (address < 8 && address != 2 && address != 7) {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 upd->port_data[address] = value;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 } else {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 switch (address)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 {
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
245 case 0x00:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
246 case 0x01:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
247 case 0x03:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
248 case 0x04:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
249 case 0x05:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
250 case 0x06:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
251 printf("P%X: %02X\n", address & 7, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
252 upd->port_data[address & 7] = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
253 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
254 case 0x10:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
255 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
256 upd->cr00 &= 0xFF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
257 upd->cr00 |= value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
258 printf("CR00: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
259 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
260 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
261 case 0x11:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
262 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
263 upd->cr00 &= 0xFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
264 upd->cr00 |= value << 8;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
265 printf("CR00: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
266 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
267 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
268 case 0x12:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
269 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
270 upd->cr01 &= 0xFF00;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
271 upd->cr01 |= value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
272 printf("CR01: %04X\n", upd->cr00);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
273 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
274 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
275 case 0x13:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
276 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
277 upd->cr01 &= 0xFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
278 upd->cr01 |= value << 8;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
279 printf("CR01: %04X\n", upd->cr01);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
280 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
281 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
282 case 0x14:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
283 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
284 upd->cr10 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
285 printf("CR10: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
286 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
287 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
288 case 0x1C:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
289 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
290 upd->cr11 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
291 printf("CR11: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
292 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
293 break;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 case 0x20:
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
295 case 0x21:
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 case 0x23:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 case 0x25:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 case 0x26:
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
299 printf("PM%X: %02X\n", address & 0x7, value);
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 upd->port_mode[address & 7] = value;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 break;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
302 case 0x30:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
303 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
304 upd->crc0 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
305 printf("CRC0 CLR01: %X, MOD: %X, Other: %X\n", value >> 3 & 1, value >> 6, value & 0x37);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
306 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
307 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
308 case 0x32:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
309 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
310 upd->crc1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
311 printf("CRC1 CLR11: %X, CM: %X, CLR10: %X\n", value >> 3 & 1, value >> 2 & 1, value >> 1 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
312 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
313 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
314 case 0x40:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
315 upd->puo = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
316 printf("PUO: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
317 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
318 case 0x43:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
319 upd->pmc3 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
320 printf("PMC3 TO: %X, SO: %X, SCK: %X, TxD: %X, RxD: %X\n", value >> 4, value >> 3 & 1, value >> 2 & 1, value >> 1 & 1, value & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
321 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
322 case 0x5D:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
323 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
324 upd->tmc0 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
325 printf("TMC0 CE0: %X, OVF0: %X - TM3 CE3: %X\n", value >> 3 & 1, value >> 2 & 1, value >> 7 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
326 if (!(value & 0x8)) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
327 upd->tm0 = 0;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
328 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
329 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
330 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
331 case 0x5E:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
332 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
333 upd->prm1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
334 printf("PRM1: %02X\n", value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
335 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
336 break;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
337 case 0x5F:
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
338 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
339 upd->tmc1 = value;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
340 printf("TMC1 CE2: %X, OVF2: %X, CMD2: %X, CE1: %X, OVF1: %X\n", value >> 7, value >> 6 & 1, value >> 5 & 1, value >> 3 & 1, value >> 2 & 1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
341 upd78k2_calc_next_int(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
342 break;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 case 0xC4:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 upd->mm = value;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 break;
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
346 case 0xE0:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
347 upd->if0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
348 upd->if0 |= value;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
349 upd78k2_calc_next_int(upd);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
350 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
351 case 0xE1:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
352 upd->if0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
353 upd->if0 |= value << 8;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
354 upd78k2_calc_next_int(upd);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
355 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
356 case 0xE4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
357 upd->mk0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
358 upd->mk0 |= value;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
359 printf("MK0: %04X (low: %02X)\n", upd->mk0, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
360 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
361 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
362 case 0xE5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
363 upd->mk0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
364 upd->mk0 |= value << 8;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
365 printf("MK0: %04X (hi: %02X)\n", upd->mk0, value);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
366 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
367 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
368 case 0xE8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
369 upd->pr0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
370 upd->pr0 |= value;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
371 printf("PR0: %04X\n", upd->pr0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
372 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
373 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
374 case 0xE9:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
375 upd->pr0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
376 upd->pr0 |= value << 8;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
377 printf("PR0: %04X\n", upd->pr0);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
378 upd78k2_sync_cycle(upd, upd->sync_cycle);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
379 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
380 case 0xEC:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
381 upd->ism0 &= 0xFF00;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
382 upd->ism0 |= value;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
383 printf("ISM0: %04X\n", upd->ism0);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
384 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
385 case 0xED:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
386 upd->ism0 &= 0xFF;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
387 upd->ism0 |= value << 8;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
388 printf("ISM0: %04X\n", upd->ism0);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
389 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
390 case 0xF4:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
391 upd->intm0 = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
392 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
393 case 0xF5:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
394 upd->intm1 = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
395 break;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
396 case 0xF8:
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
397 upd->ist = value;
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
398 break;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 default:
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 fprintf(stderr, "Unhandled uPD78237 SFR write %02X: %02X\n", address, value);
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 break;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 return context;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 void init_upd78k2_opts(upd78k2_options *opts, memmap_chunk const *chunks, uint32_t num_chunks)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 memset(opts, 0, sizeof(*opts));
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 opts->gen.memmap = chunks;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 opts->gen.memmap_chunks = num_chunks;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 opts->gen.address_mask = 0xFFFFF;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 opts->gen.max_address = 0xFFFFF;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
414 opts->gen.clock_divider = 1;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 upd78k2_context *init_upd78k2_context(upd78k2_options *opts)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 {
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 upd78k2_context *context = calloc(1, sizeof(upd78k2_context));
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 context->opts = opts;
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
421 memset(context->port_mode, 0xFF, sizeof(context->port_mode));
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
422 context->crc0 = 0x10;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
423 context->mm = 0x20;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
424 context->mk0 = 0xFFFF;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
425 context->pr0 = 0xFFFF;
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 return context;
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 }
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
429 void upd78k2_sync_cycle(upd78k2_context *upd, uint32_t target_cycle)
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
430 {
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
431 upd78k2_update_timer0(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
432 upd78k2_update_timer1(upd);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
433 upd->sync_cycle = target_cycle;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
434 upd78k2_calc_next_int(upd);
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
435 }
2713
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
436
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
437 void upd78k2_calc_vector(upd78k2_context *upd)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
438 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
439 uint32_t pending_enabled = upd->scratch1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
440 uint32_t vector = 0x6;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
441 while (pending_enabled)
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
442 {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
443 if (pending_enabled & 1) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
444 upd->scratch1 = vector;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
445 return;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
446 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
447 pending_enabled >>= 1;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
448 vector += 2;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
449 if (vector == 0xE) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
450 vector = 0x14;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
451 } else if (vector == 0x20) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
452 vector = 0xE;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
453 } else if (vector == 0x14) {
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
454 vector = 0x20;
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
455 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
456 }
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
457 fatal_error("upd78k2_calc_vector: %X\n", upd->scratch1);
a88eff3fb5d8 Initial stab at uPDK78K/II timer 0, timer 1 and corresponding interrupts
Michael Pavone <pavone@retrodev.com>
parents: 2706
diff changeset
458 }