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annotate test.s68 @ 622:b76d2a628ab9

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Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
author Michael Pavone <pavone@retrodev.com>
date Tue, 17 Jun 2014 19:01:01 -0700
parents 3adbd97f71f2
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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45
3adbd97f71f2 Add vector table to test.s68
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1 dc.l $0, start
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2 dc.l start
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3 dc.l start
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4 dc.l start
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5 dc.l start
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6 dc.l start
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7 dc.l start
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8 dc.l start
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9 dc.l start
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10 dc.l start
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11 dc.l start
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12 dc.l start
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13 dc.l start
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14 dc.l start
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15 dc.l start
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16 dc.l start
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17 dc.l start
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18 dc.l start
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19 dc.l start
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20 dc.l start
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21 dc.l start
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22 dc.l start
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23 dc.l start
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24 dc.l after
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25 dc.l after
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26 dc.l after
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27 dc.l after
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28 dc.l after
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29 dc.l after
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30 dc.l after
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31 dc.l after
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32
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33 start:
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34 bra after
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35 after:
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
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36 abcd d0, d1
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37 abcd -(a2), -(a3)
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38 add.b #42, d1
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39 add.w d3, d4
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40 add.l d5, (a0)+
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41 addq.w #5, d0
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42 addx d6, d7
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43 addx -(a4), -(a5)
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44 and.w d5, d7
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45 andi.l #5, (a0)+
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46 andi #8, CCR
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47 andi #9, CCR
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48 foo:
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49 asl d0, d3
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50 asr #3, d7
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51 bne foo
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52 bchg #5, d0
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53 bclr #7, d0
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54 bset #1, d0
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55 bsr bar
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56 btst #3, d0
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57 chk.w #53, d7
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58 clr d5
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59 cmp d0, d1
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60 bar:
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61 dbra d0, bar
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62 divs.w d5, d7
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63 divu.w d3, d4
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64 eor.w d0, d6
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65 eori.l #5, d2
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66 eori #5, ccr
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67 eori #2700, sr
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68 exg d5, d6
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69 ext d2
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70 illegal
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71 jmp (a0)
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72 jsr (a5)
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73 lea (a0, 8), a3
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74 link.w a6, #32
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75 lsl d0, d3
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76 lsr #3, d7
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77 move.b (a0)+, (32, a5)
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78 moveq #5, d0
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79 move #89, ccr
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80 move sr, d0
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81 move #2700, sr
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82 move a5, usp
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83 movem.l d0-d3/a4/a6, -(a7)
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84 movep.w d4, (40, a3)
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85 muls.w d6, d7
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86 mulu.w d2, d4
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87 nbcd -(a2)
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88 neg.l d7
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89 negx.b d5
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90 nop
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91 not.b d3
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92 or.w d5, d7
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93 ori.b #7, d5
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94 ori #5, ccr
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95 ori #2700, sr
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96 pea (24, a3)
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97 reset
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98 rol.l #7, d0
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99 rol.w d5, d0
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100 ror.w d1, d3
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101 roxl.l #7, d0
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102 roxl.w d5, d0
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103 roxr.w d1, d3
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104 rte
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105 rtr
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106 rts
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107 sbcd d0, d1
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108 sbcd -(a2), -(a3)
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109 slt d5
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110 stop #3
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111 sub.b #42, d1
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112 sub.w d3, d4
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113 sub.l d5, (a0)+
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114 subq.w #5, d0
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115 subx d6, d7
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116 subx -(a4), -(a5)
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Mike Pavone <pavone@retrodev.com>
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117 swap d6
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Mike Pavone <pavone@retrodev.com>
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118 tas (a3)
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Mike Pavone <pavone@retrodev.com>
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119 trap #7
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120 trapv
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121 tst.w (a4)+
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122 unlk a6
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123