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changeset 12:db60ed283d8d

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Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
author Mike Pavone <pavone@retrodev.com>
date Thu, 15 Nov 2012 00:52:53 -0800
parents d5e9bac9ebdf
children 168b1a873895
files 68kinst.c test.s68
diffstat 2 files changed, 112 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/68kinst.c	Wed Nov 14 23:04:55 2012 -0800
+++ b/68kinst.c	Thu Nov 15 00:52:53 2012 -0800
@@ -123,8 +123,31 @@
 			}
 			decoded->src.addr_mode = MODE_REG;
 			decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
+			decoded->extra.size = OPSIZE_LONG;
 			istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst));
 		} else if ((*istream & 0xF00) == 0x800) {
+			//BTST, BCHG, BCLR, BSET
+			switch ((*istream >> 6) & 0x3)
+			{
+			case 0:
+				decoded->op = M68K_BTST;
+				break;
+			case 1:
+				decoded->op = M68K_BCHG;
+				break;
+			case 2:
+				decoded->op = M68K_BCLR;
+				break;
+			case 3:
+				decoded->op = M68K_BSET;
+				break;
+			}
+			opmode = (*istream >> 3) & 0x7;
+			reg = *istream & 0x7;
+			decoded->src.addr_mode = MODE_IMMEDIATE;
+			decoded->src.params.u8 = *(++istream);
+			decoded->extra.size = OPSIZE_BYTE;
+			istream = m68k_decode_op_ex(istream, opmode, reg, OPSIZE_BYTE, &(decoded->dst));
 		} else if ((*istream & 0xC0) == 0xC0) {
 #ifdef M68020
 			//CMP2, CHK2, CAS, CAS2, RTM, CALLM
@@ -1090,7 +1113,7 @@
 	"trap",
 	"trapv",
 	"tst",
-	"unlnk",
+	"unlk",
 	"invalid"
 };
 
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test.s68	Thu Nov 15 00:52:53 2012 -0800
@@ -0,0 +1,88 @@
+	abcd d0, d1
+	abcd -(a2), -(a3)
+	add.b #42, d1
+	add.w d3, d4
+	add.l d5, (a0)+
+	addq.w #5, d0
+	addx d6, d7
+	addx -(a4), -(a5)
+	and.w d5, d7
+	andi.l #5, (a0)+
+	andi #8, CCR
+	andi #9, CCR
+foo:
+	asl d0, d3
+	asr #3, d7
+	bne foo
+	bchg #5, d0
+	bclr #7, d0
+	bset #1, d0
+	bsr bar
+	btst #3, d0
+	chk.w #53, d7
+	clr d5
+	cmp d0, d1
+bar:
+	dbra d0, bar
+	divs.w d5, d7
+	divu.w d3, d4
+	eor.w d0, d6
+	eori.l #5, d2
+	eori #5, ccr
+	eori #2700, sr
+	exg d5, d6
+	ext d2
+	illegal
+	jmp (a0)
+	jsr (a5)
+	lea (a0, 8), a3
+	link.w a6, #32
+	lsl d0, d3
+	lsr #3, d7
+	move.b (a0)+, (32, a5)
+	moveq  #5, d0
+	move #89, ccr
+	move sr, d0
+	move #2700, sr
+	move a5, usp
+	movem.l d0-d3/a4/a6, -(a7)
+	movep.w d4, (40, a3)
+	muls.w d6, d7
+	mulu.w d2, d4
+	nbcd -(a2)
+	neg.l d7
+	negx.b d5
+	nop
+	not.b d3
+	or.w d5, d7
+	ori.b #7, d5
+	ori #5, ccr
+	ori #2700, sr
+	pea (24, a3)
+	reset
+	rol.l #7, d0
+	rol.w d5, d0
+	ror.w d1, d3
+	roxl.l #7, d0
+	roxl.w d5, d0
+	roxr.w d1, d3
+	rte
+	rtr
+	rts
+	sbcd d0, d1
+	sbcd -(a2), -(a3)
+	slt d5
+	stop #3
+	sub.b #42, d1
+	sub.w d3, d4
+	sub.l d5, (a0)+
+	subq.w #5, d0
+	subx d6, d7
+	subx -(a4), -(a5)
+	swap d6
+	tas (a3)
+	trap #7
+	trapv
+	tst.w (a4)+
+	unlk a6
+